From owner-svn-src-head@FreeBSD.ORG Sun Aug 3 21:56:54 2014 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 559C8B0C for ; Sun, 3 Aug 2014 21:56:54 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 299042519 for ; Sun, 3 Aug 2014 21:56:54 +0000 (UTC) Received: from gavin (uid 1136) (envelope-from gavin@FreeBSD.org) id 5b05 by svn.freebsd.org (DragonFly Mail Agent v0.9+); Sun, 03 Aug 2014 21:56:54 +0000 From: Gavin Atkinson Date: Sun, 3 Aug 2014 21:56:54 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r269488 - head/sys/dev/pccbb X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Message-Id: <53deb026.5b05.3dd68e61@svn.freebsd.org> X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 03 Aug 2014 21:56:54 -0000 Author: gavin Date: Sun Aug 3 21:56:53 2014 New Revision: 269488 URL: http://svnweb.freebsd.org/changeset/base/269488 Log: For reasons which are not clear, r254263 broke some PCMCIA and CardBus bridges in strange ways, either rendering them unable to detect insertion and removal events, or possibly unable to read from the device behind the bridge. This fixes at least one laptop, a Toshiba Tecra M5 with a Texas Instruments PCxx12 (d=0x8039 v=0c104c) bridge. The very similar Tecra M9 has the same bridge, but worked fine without this change. The bridge chip has no I/O port BAR, and there is nothing in the spec to suggest I/O decoding should be enabled; however enabling it fixes the issue. Add an XXX comment to this effect. Discussed with: jhb, imp MFC after: 2 weeks Modified: head/sys/dev/pccbb/pccbb_pci.c Modified: head/sys/dev/pccbb/pccbb_pci.c ============================================================================== --- head/sys/dev/pccbb/pccbb_pci.c Sun Aug 3 21:54:22 2014 (r269487) +++ head/sys/dev/pccbb/pccbb_pci.c Sun Aug 3 21:56:53 2014 (r269488) @@ -481,6 +481,8 @@ cbb_chipinit(struct cbb_softc *sc) /* Enable memory access */ pci_enable_busmaster(sc->dev); + /* XXX: This should not be necessary, but some chipsets require it */ + PCI_MASK_CONFIG(sc->dev, PCIR_COMMAND, | PCIM_CMD_PORTEN, 2); /* disable Legacy IO */ switch (sc->chipset) {