From owner-svn-src-all@FreeBSD.ORG Thu Jan 21 02:21:32 2010 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 38322106566C; Thu, 21 Jan 2010 02:21:32 +0000 (UTC) (envelope-from neel@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 27E8F8FC16; Thu, 21 Jan 2010 02:21:32 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id o0L2LW1l088541; Thu, 21 Jan 2010 02:21:32 GMT (envelope-from neel@svn.freebsd.org) Received: (from neel@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id o0L2LWHE088539; Thu, 21 Jan 2010 02:21:32 GMT (envelope-from neel@svn.freebsd.org) Message-Id: <201001210221.o0L2LWHE088539@svn.freebsd.org> From: Neel Natu Date: Thu, 21 Jan 2010 02:21:32 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r202732 - head/sys/mips/mips X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jan 2010 02:21:32 -0000 Author: neel Date: Thu Jan 21 02:21:31 2010 New Revision: 202732 URL: http://svn.freebsd.org/changeset/base/202732 Log: Get rid of redundant setting of interrupt enable bit when restoring the status register from the PCB. Remove a couple of misleading comments while I am here. The comments are misleading because they imply that interrupts will be enabled after the status register is restored from the PCB. This is not the case because the processor is at the exception level (SR_EXL is set). Approved by: imp (mentor) Modified: head/sys/mips/mips/exception.S Modified: head/sys/mips/mips/exception.S ============================================================================== --- head/sys/mips/mips/exception.S Thu Jan 21 00:54:22 2010 (r202731) +++ head/sys/mips/mips/exception.S Thu Jan 21 02:21:31 2010 (r202732) @@ -581,16 +581,10 @@ NNON_LEAF(MipsUserGenException, STAND_FR #ifdef TARGET_OCTEON and k0, k0, ~(MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX) #endif - or k0, k0, (MIPS_SR_INT_IE) .set noat RESTORE_U_PCB_REG(AT, AST, k1) -/* - * The restoration of the user SR must be done only after - * k1 is no longer needed. Otherwise, k1 will get clobbered after - * interrupts are enabled. - */ - mtc0 k0, COP_0_STATUS_REG # still exeption level + mtc0 k0, COP_0_STATUS_REG # still exception level ITLBNOPFIX sync eret @@ -814,15 +808,9 @@ NNON_LEAF(MipsUserIntr, STAND_FRAME_SIZE #ifdef TARGET_OCTEON and k0, k0, ~(MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX) #endif - or k0, k0, (MIPS_SR_INT_IE|SR_EXL) .set noat RESTORE_U_PCB_REG(AT, AST, k1) -/* - * The restoration of the user SR must be done only after - * k1 is no longer needed. Otherwise, k1 will get clobbered after - * interrupts are enabled. - */ mtc0 k0, COP_0_STATUS_REG # SR with EXL set. ITLBNOPFIX sync