From owner-svn-src-stable-10@FreeBSD.ORG Mon Sep 22 20:10:46 2014 Return-Path: Delivered-To: svn-src-stable-10@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 451CA6D0; Mon, 22 Sep 2014 20:10:46 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 2F870C0; Mon, 22 Sep 2014 20:10:46 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.9/8.14.9) with ESMTP id s8MKAkGc094750; Mon, 22 Sep 2014 20:10:46 GMT (envelope-from marcel@FreeBSD.org) Received: (from marcel@localhost) by svn.freebsd.org (8.14.9/8.14.9/Submit) id s8MKAkpT094749; Mon, 22 Sep 2014 20:10:46 GMT (envelope-from marcel@FreeBSD.org) Message-Id: <201409222010.s8MKAkpT094749@svn.freebsd.org> X-Authentication-Warning: svn.freebsd.org: marcel set sender to marcel@FreeBSD.org using -f From: Marcel Moolenaar Date: Mon, 22 Sep 2014 20:10:46 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-10@freebsd.org Subject: svn commit: r271998 - stable/10/sys/ia64/ia64 X-SVN-Group: stable-10 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-stable-10@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: SVN commit messages for only the 10-stable src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 22 Sep 2014 20:10:46 -0000 Author: marcel Date: Mon Sep 22 20:10:45 2014 New Revision: 271998 URL: http://svnweb.freebsd.org/changeset/base/271998 Log: Make sure all memory updates are made visible before we let go of the thread in cpu_switch(). It's otherwise possible that on another CPU the thread continues from stale context data. Note that this is prominent on newer CPUs, like the Montecito, that really take advantage of the weak memory ordering. First generation Itanium 2 is not that aggressive and does not need this. This is a direct commit to stable/10. Approved by: re@ (gjb) Modified: stable/10/sys/ia64/ia64/machdep.c Modified: stable/10/sys/ia64/ia64/machdep.c ============================================================================== --- stable/10/sys/ia64/ia64/machdep.c Mon Sep 22 20:04:59 2014 (r271997) +++ stable/10/sys/ia64/ia64/machdep.c Mon Sep 22 20:10:45 2014 (r271998) @@ -465,6 +465,8 @@ cpu_switch(struct thread *old, struct th oldpcb->pcb_current_pmap = pmap_switch(newpcb->pcb_current_pmap); + ia64_mf(); + atomic_store_rel_ptr(&old->td_lock, mtx); #if defined(SCHED_ULE) && defined(SMP)