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From: Pawel Pekala <pawel@FreeBSD.org>
Date: Wed, 27 Jul 2016 17:04:44 +0000 (UTC)
To: ports-committers@freebsd.org, svn-ports-all@freebsd.org,
 svn-ports-head@freebsd.org
Subject: svn commit: r419189 - head/cad/p5-Verilog-Perl
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Author: pawel
Date: Wed Jul 27 17:04:44 2016
New Revision: 419189
URL: https://svnweb.freebsd.org/changeset/ports/419189

Log:
  - Change maintainer email [1]
  - Add LICENSE info [1]
  - Strip more binaries [1]
  - No need to include bsd.port.pre.mk
  
  PR:		210844 [1]
  Submitted by:	otacilio.neto@bsd.com.br (maintainer)

Modified:
  head/cad/p5-Verilog-Perl/Makefile

Modified: head/cad/p5-Verilog-Perl/Makefile
==============================================================================
--- head/cad/p5-Verilog-Perl/Makefile	Wed Jul 27 17:02:30 2016	(r419188)
+++ head/cad/p5-Verilog-Perl/Makefile	Wed Jul 27 17:04:44 2016	(r419189)
@@ -7,9 +7,11 @@ CATEGORIES=	cad perl5
 MASTER_SITES=	CPAN
 PKGNAMEPREFIX=	p5-
 
-MAINTAINER=	otacilio.neto@ee.ufcg.edu.br
+MAINTAINER=	otacilio.neto@bsd.com.br
 COMMENT=	Building point for Verilog support in the Perl language
 
+LICENSE=	LGPL3
+
 BUILD_DEPENDS=	flex>=2.5.35:textproc/flex
 
 USES=		bison gmake perl5
@@ -18,12 +20,11 @@ CONFIGURE_ENV=	CXX=${CXX}\
 		CPP=${CPP}\
 		CC=${CC}
 
-.include <bsd.port.pre.mk>
-
 post-install:
 	${STRIP_CMD} ${STAGEDIR}${PREFIX}/${SITE_ARCH_REL}/auto/Verilog/Parser/*.so
+	${STRIP_CMD} ${STAGEDIR}${PREFIX}/${SITE_ARCH_REL}/auto/Verilog/Preproc/*.so
 
 regression-test: build
 	make test -C ${WRKSRC}
 
-.include <bsd.port.post.mk>
+.include <bsd.port.mk>