From owner-cvs-all@FreeBSD.ORG Wed May 26 20:33:03 2004 Return-Path: Delivered-To: cvs-all@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 0217A16A4CE; Wed, 26 May 2004 20:33:03 -0700 (PDT) Received: from mailout2.pacific.net.au (mailout2.pacific.net.au [61.8.0.85]) by mx1.FreeBSD.org (Postfix) with ESMTP id 43FF443D41; Wed, 26 May 2004 20:33:02 -0700 (PDT) (envelope-from bde@zeta.org.au) Received: from mailproxy1.pacific.net.au (mailproxy1.pacific.net.au [61.8.0.86])i4R3WW5v007228; Thu, 27 May 2004 13:32:32 +1000 Received: from gamplex.bde.org (katana.zip.com.au [61.8.7.246]) i4R3WU2O019026; Thu, 27 May 2004 13:32:31 +1000 Date: Thu, 27 May 2004 13:32:29 +1000 (EST) From: Bruce Evans X-X-Sender: bde@gamplex.bde.org To: Thomas Moestl In-Reply-To: <200405262159.i4QLx1cQ072334@repoman.freebsd.org> Message-ID: <20040527123826.R8527@gamplex.bde.org> References: <200405262159.i4QLx1cQ072334@repoman.freebsd.org> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII cc: cvs-src@FreeBSD.org cc: src-committers@FreeBSD.org cc: cvs-all@FreeBSD.org Subject: Re: cvs commit: src/sys/dev/uart uart_dev_ns8250.c X-BeenThere: cvs-all@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: CVS commit messages for the entire tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 27 May 2004 03:33:03 -0000 On Wed, 26 May 2004, Thomas Moestl wrote: > tmm 2004/05/26 14:59:01 PDT > > FreeBSD src repository > > Modified files: > sys/dev/uart uart_dev_ns8250.c > Log: > It seems that clearing the MCR_IE bit in the modem control register > does not reliably prevent the triggering of interrupts for all supported > configurations. Thus, the FIFO size probe could cause an interrupt, > which could lead to an interrupt storm in the shared interrupt case. s/It seems that clearing/Clearing/. Clearing MCR_IE disables the device's line driver for the irq. At least on old i386 isa systems, the line driver is normally connected to a tri-state latch which floats high due to a weak pullup when all its inputs are disabled. So "disabling" interrupts by clearing MCR_IE normally _causes_ exactly one interrupt on old i386 isa systems with edge-sensitive interrupts. If the interrupt is level-senstive and floats high, then it should be active-low so that there is not an interrupt storm from the spurious interrupt (and not even a single spurious interrupt) for the level-sensitive case. However, the buggy uart probe probably caused interrupt storms determistically for non-spurious interrupts as follows: - have a shared irq with one device already using it attached - cause an interrupt in the probe - the interrupt is enabled for the other device(s) attached to it, so it gets sent to the interrupt handler, but the interrupt handler can't handle it because the device that generated it isn't attached yet. The sio driver needs to generate interrupts in the probe for other reasons. It tries to avoid the problem by disabling CPU interrupts. This works right in the !SMP case, and I think it works well enough in the SMP case too. In the SMP case, other CPUs may see the interrupt, but if it is shared with an sio device then they will block and not see a storm; if it is shared with a non-sio device, then they may see a storm. In both cases, the CPU running the probe is unaffected and eventually handles the interrupt, so the interrupt or storm seen by the other CPUs goes away. Bruce