Date: Fri, 10 Dec 2021 12:59:04 -0800 From: Mark Millard via freebsd-arm <freebsd-arm@freebsd.org> To: =?utf-8?Q?Kornel_Dul=C4=99ba?= <mindal@semihalf.com> Cc: Emmanuel Vadot <manu@bidouilliste.com>, Peter Jeremy <peterj@freebsd.org>, Andriy Gapon <avg@FreeBSD.org>, Free BSD <freebsd-arm@freebsd.org>, "wma@freebsd.org" <wma@freebsd.org> Subject: Re: Rock64 configuration fails to boot for main 22c4ab6cb015 but worked for main 06bd74e1e39c (Nov 21): e.MMC mishandled? Message-ID: <21B0478B-340F-4BB2-9189-B5A6AE458134@yahoo.com> In-Reply-To: <CAKpxNiyzKF_JgMFEPK00jU=%2B9_qUq3Vg9KzSos8oCXNs2%2BPYyw@mail.gmail.com> References: <243CBFC7-DFB5-4F8B-A8A3-CFF78455148D.ref@yahoo.com> <243CBFC7-DFB5-4F8B-A8A3-CFF78455148D@yahoo.com> <20211209081930.7970b6995a8f7c5f7466227d@bidouilliste.com> <053617FD-AA34-4A3F-853A-4D2E44F8254B@yahoo.com> <43901D57-9C39-4FAC-A2BE-CCE642791705@yahoo.com> <CAKpxNiwxvs7-%2BsNa1mX8rAUy_Bs4FdE1%2Bamf5hZXB9CehEJdwQ@mail.gmail.com> <8DAA50A1-3CF0-4AFA-9977-58FE15D4F171@yahoo.com> <CAKpxNiyzKF_JgMFEPK00jU=%2B9_qUq3Vg9KzSos8oCXNs2%2BPYyw@mail.gmail.com>
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On 2021-Dec-10, at 01:51, Kornel Dul=C4=99ba <mindal@semihalf.com> = wrote: > On Thu, Dec 9, 2021 at 11:54 PM Mark Millard <marklmi@yahoo.com> = wrote: >>=20 . . . [History deleted] . . . >> Well, I've tried Armbian 21.08 (Linux 5.10.60-rockchip64) and its = first >> boot reports the sequence ended up using HS200 at 150 MHz: >>=20 >> # dmesg | grep mmc >> [ 3.195642] vcc18_emmc: supplied by vcc_io >> [ 3.227180] dwmmc_rockchip ff520000.mmc: IDMAC supports 32-bit = address mode. >> [ 3.227187] dwmmc_rockchip ff500000.mmc: IDMAC supports 32-bit = address mode. >> [ 3.227225] dwmmc_rockchip ff520000.mmc: Using internal DMA = controller. >> [ 3.227234] dwmmc_rockchip ff500000.mmc: Using internal DMA = controller. >> [ 3.227244] dwmmc_rockchip ff520000.mmc: Version ID is 270a >> [ 3.227259] dwmmc_rockchip ff500000.mmc: Version ID is 270a >> [ 3.227342] dwmmc_rockchip ff520000.mmc: DW MMC controller at irq = 42,32 bit host data width,256 deep fifo >> [ 3.227390] dwmmc_rockchip ff500000.mmc: DW MMC controller at irq = 41,32 bit host data width,256 deep fifo >> [ 3.229762] mmc_host mmc0: card is non-removable. >> [ 3.241627] mmc_host mmc1: Bus speed (slot 0) =3D 400000Hz (slot = req 400000Hz, actual 400000HZ div =3D 0) >> [ 3.241860] mmc_host mmc0: Bus speed (slot 0) =3D 400000Hz (slot = req 400000Hz, actual 400000HZ div =3D 0) >>=20 >> Note the below 3 lines: >=20 >>=20 >> [ 3.327640] mmc_host mmc0: Bus speed (slot 0) =3D 150000000Hz = (slot req 150000000Hz, actual 150000000HZ div =3D 0) >> [ 3.730166] dwmmc_rockchip ff520000.mmc: Successfully tuned phase = to 245 >> [ 3.730397] mmc0: new HS200 MMC card at address 0001 >>=20 >> Note the "tuned phase to 245" as part of that. >=20 > Yep, it looks like in Linux they're doing some custom tuning logic > specific to this controller. > FreeBSD only executes generic tuning code, which apparently is not = enough. Based on this and some more exchanges with Andriy off list, I went looking in Linux source, something I'd been avoiding. Sure enough: dw_mci_rk3288_execute_tuning explores, looking for the widest range of phase settings that work and picking the middle of the range as the value to leave in place. That code is what generates the "Successfully tuned phase to" notice that Linux was reporting. (There is a default used if all settings work.) The code for doing this uses CMD21 to evaluate the phase settings. If this sort of thing is (sometimes?) normal (to have some context-specific implicit parameter assignment involved for the CMD21 use), I've not yet noticed how FreeBSD allows for getting to device-specific code that establishes the assignment.=20 But, clearly, I'm far from knowledgable about how things work/fit. I've just been reading understand some about the problem. >>=20 >> [ 3.732538] mmcblk0: mmc0:0001 DJNB4R 116 GiB >> [ 3.733510] mmcblk0boot0: mmc0:0001 DJNB4R partition 1 4.00 MiB >> [ 3.734513] mmcblk0boot1: mmc0:0001 DJNB4R partition 2 4.00 MiB >> [ 3.734917] mmcblk0rpmb: mmc0:0001 DJNB4R partition 3 4.00 MiB, = chardev (243:0) >> [ 3.746005] mmcblk0: p1 >> [ 4.880861] EXT4-fs (mmcblk0p1): mounted filesystem with writeback = data mode. Opts: (null) >> [ 6.686795] EXT4-fs (mmcblk0p1): re-mounted. Opts: = commit=3D600,errors=3Dremount-ro >> [ 12.767622] EXT4-fs (mmcblk0p1): resizing filesystem from 479232 = to 30224384 blocks >> [ 22.791358] EXT4-fs (mmcblk0p1): resized to 16252928 blocks >> [ 31.531320] EXT4-fs (mmcblk0p1): resized filesystem to 30224384 >>=20 >> So, as far as I can tell, if FreeBSD wants to support HS200 at 150 = MHz >> on the Rock64, it can be done, voltage changing and tuning apparently >> involved. >>=20 >> That is not to say that any FreeBSD developer wants to be supporting = such. >> Sticking to 52 MHz and possibly 3V for the Rock 64 eMMC use would = again >> make things operational. >=20 > Yes, imho marking HS200 in this controller as broken is the right > choice, unless someone(TM) writes the missing code. Seems appropriate to me. >> I'll note that Armbian's U-Boot reports itself as: >>=20 >> U-Boot 2020.10-armbian (Aug 08 2021 - 18:02:43 +0200) >>=20 >> I'll also note that rebooting swapped which was mmc0 vs. mmc1: >>=20 >> # dmesg | grep mmc >> [ 3.198267] vcc18_emmc: supplied by vcc_io >> [ 3.229498] dwmmc_rockchip ff500000.mmc: IDMAC supports 32-bit = address mode. >> [ 3.229547] dwmmc_rockchip ff500000.mmc: Using internal DMA = controller. >> [ 3.229566] dwmmc_rockchip ff500000.mmc: Version ID is 270a >> [ 3.229665] dwmmc_rockchip ff500000.mmc: DW MMC controller at irq = 41,32 bit host data width,256 deep fifo >> [ 3.229762] dwmmc_rockchip ff520000.mmc: IDMAC supports 32-bit = address mode. >> [ 3.229799] dwmmc_rockchip ff520000.mmc: Using internal DMA = controller. >> [ 3.229817] dwmmc_rockchip ff520000.mmc: Version ID is 270a >> [ 3.229896] dwmmc_rockchip ff520000.mmc: DW MMC controller at irq = 42,32 bit host data width,256 deep fifo >> [ 3.231547] mmc_host mmc1: card is non-removable. >> [ 3.243883] mmc_host mmc0: Bus speed (slot 0) =3D 400000Hz (slot = req 400000Hz, actual 400000HZ div =3D 0) >> [ 3.244767] mmc_host mmc1: Bus speed (slot 0) =3D 400000Hz (slot = req 400000Hz, actual 400000HZ div =3D 0) >> [ 3.327505] mmc_host mmc1: Bus speed (slot 0) =3D 150000000Hz = (slot req 150000000Hz, actual 150000000HZ div =3D 0) >> [ 3.834347] dwmmc_rockchip ff520000.mmc: Successfully tuned phase = to 251 >> [ 3.834477] mmc1: new HS200 MMC card at address 0001 >> [ 3.836188] mmcblk1: mmc1:0001 DJNB4R 116 GiB >> [ 3.837140] mmcblk1boot0: mmc1:0001 DJNB4R partition 1 4.00 MiB >> [ 3.838155] mmcblk1boot1: mmc1:0001 DJNB4R partition 2 4.00 MiB >> [ 3.838599] mmcblk1rpmb: mmc1:0001 DJNB4R partition 3 4.00 MiB, = chardev (243:0) >> [ 3.841290] mmcblk1: p1 >> [ 4.876902] EXT4-fs (mmcblk1p1): mounted filesystem with writeback = data mode. Opts: (null) >> [ 6.614516] EXT4-fs (mmcblk1p1): re-mounted. Opts: = commit=3D600,errors=3Dremount-ro >>=20 >=20 =3D=3D=3D Mark Millard marklmi at yahoo.com ( dsl-only.net went away in early 2018-Mar)
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