From owner-freebsd-mips@FreeBSD.ORG Tue Apr 20 22:04:40 2010 Return-Path: Delivered-To: freebsd-mips@FreeBSD.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 1704F1065676 for ; Tue, 20 Apr 2010 22:04:40 +0000 (UTC) (envelope-from imp@bsdimp.com) Received: from harmony.bsdimp.com (bsdimp.com [199.45.160.85]) by mx1.freebsd.org (Postfix) with ESMTP id BA7308FC29 for ; Tue, 20 Apr 2010 22:04:39 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by harmony.bsdimp.com (8.14.3/8.14.1) with ESMTP id o3KLuKwK072868; Tue, 20 Apr 2010 15:56:20 -0600 (MDT) (envelope-from imp@bsdimp.com) Date: Tue, 20 Apr 2010 15:56:33 -0600 (MDT) Message-Id: <20100420.155633.1075901050443800973.imp@bsdimp.com> To: neelnatu@gmail.com From: "M. Warner Losh" In-Reply-To: References: X-Mailer: Mew version 6.3 on Emacs 22.3 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=iso-8859-1 Content-Transfer-Encoding: quoted-printable Cc: freebsd-mips@FreeBSD.org Subject: Re: SMP support for XLR processors. X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 20 Apr 2010 22:04:40 -0000 In message: Neel Natu writes: : Hi JC, : = : On Sat, Apr 17, 2010 at 3:40 PM, C. Jayachandran : wrote: : > I've a set of initial patches to enable SMP for RMI processors. It : > comes up in multi-user with 32 CPUs. =A0I could do buildworld befor= e I : > updated to HEAD - with head there is a hang during buildworld which= : > I'm looking at, but I think the initial work can be checked in. : > : > Neel, can you have a look at the first two patches - one is to enab= le : > ULE scheduler and the second one is to move platform_init_ap to : > slightly later in the initialization sequence. : > : > The patches are : : > 1. mips-ule-support.patch : > - Enable ULE scheduler for MIPS : > : > 2. mips-smp-move-platform.patch : > - We need a hook to setup message ring and its interrupts, we use : > platform_init_ap now, and move it be called later for XLR : > : = : I would like to see us move away from #ifdef TARGET_FOO in files unde= r : mips/mips as much as possible. I think that is achieved easily in thi= s : instance. : = : How about we create a function platform_ap_enable_interrupts() that i= s : called from smp_init_secondary()? This function will be defined for : each platform. : = : In the common case this function will simply call : mips_ap_enable_interrupts() that encapsulates the logic that we : currently have to setup interrupt masks for clock and ipi interrupts : in the status register. In the XLR case however it can do something : different. : = : Ditto about the #ifdef TARGET_XLR_XLS in mpboot.S. You can simply hav= e : an empty platform_init_ap() for XLR. In general, I'd love to see the TARGET_xxx stuff die entirely in the mips tree. That's a hack inherited from the Octeon port. There's other mechanisms that are better suited for this stuff... Warner : best : Neel : = : > 3. rmi-prid.patch : > Add RMI processor ID prints - right now it prints unknown processor= .= : > : > 4. rmi-pcib-fix.patch : > XLR pci bridge should be off the IODI bus, currently it is off the : > nexus bus which will cause issue when bus_setup_intr on nexus is : > called : > : > 5. cleanup-reorg-cpuid-rge-kx.patch : > This set has a many changes rolled up: : > =A0- clean up rge driver, remove unused code paths and commented co= de : > (long way to go still) : > =A0- xlr_cpu_id(), xlr_core_id() and xlr_thr_id() updated and usage= updated : > =A0- fix a bug - we cannot use MIPS_PHYS_TO_KSEG0 on physical addre= sses : > here, I have made changes for using XKPHYS to do the same process. : > =A0- the KX bit is enabled and interrupts are disabled before the : > physical memory is read, to avoid the KX bit setting from affecting= : > other code. : > - move message ring code to on_chip.c from xlr_machdep.c, now all : > message ring code is in on_chip.c : > : > 6. rmi-xlr-smp.patch : > SMP Support for XLR : > - mpwait.S added to get the other CPUs out of bootloader code at st= artup. : > - SMP platform related functions. : > - disable shared TLB code for SMP - since threads have different ma= ppings. : > : > The patches are also available at : > http://sites.google.com/site/cjayachandran/files : > : > Enabling all 32 threads will need a minor fix in the SMP code, see = the : > patch subr_smp-fix.patch at the same place. : > : > Regards, : > JC. : > : _______________________________________________ : freebsd-mips@freebsd.org mailing list : http://lists.freebsd.org/mailman/listinfo/freebsd-mips : To unsubscribe, send any mail to "freebsd-mips-unsubscribe@freebsd.or= g" : = : =