From owner-svn-src-all@freebsd.org Wed Aug 14 16:40:24 2019 Return-Path: Delivered-To: svn-src-all@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id 32592B18F8; Wed, 14 Aug 2019 16:40:24 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) server-signature RSA-PSS (4096 bits) client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 467wLJ0WR2z4X8f; Wed, 14 Aug 2019 16:40:24 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id E33D92BAA; Wed, 14 Aug 2019 16:40:23 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id x7EGeNpk034199; Wed, 14 Aug 2019 16:40:23 GMT (envelope-from andrew@FreeBSD.org) Received: (from andrew@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id x7EGeNpc034196; Wed, 14 Aug 2019 16:40:23 GMT (envelope-from andrew@FreeBSD.org) Message-Id: <201908141640.x7EGeNpc034196@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: andrew set sender to andrew@FreeBSD.org using -f From: Andrew Turner Date: Wed, 14 Aug 2019 16:40:23 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-12@freebsd.org Subject: svn commit: r351029 - in stable/12/sys/arm64: arm64 include X-SVN-Group: stable-12 X-SVN-Commit-Author: andrew X-SVN-Commit-Paths: in stable/12/sys/arm64: arm64 include X-SVN-Commit-Revision: 351029 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 14 Aug 2019 16:40:24 -0000 Author: andrew Date: Wed Aug 14 16:40:23 2019 New Revision: 351029 URL: https://svnweb.freebsd.org/changeset/base/351029 Log: MFC r339592: Correctly set the DAIF bits in new threads We should only unmask interrupts when creating a new thread and leave the other exceptions in teh same state as before creating the thread. Modified: stable/12/sys/arm64/arm64/vm_machdep.c stable/12/sys/arm64/include/armreg.h Directory Properties: stable/12/ (props changed) Modified: stable/12/sys/arm64/arm64/vm_machdep.c ============================================================================== --- stable/12/sys/arm64/arm64/vm_machdep.c Wed Aug 14 16:12:03 2019 (r351028) +++ stable/12/sys/arm64/arm64/vm_machdep.c Wed Aug 14 16:40:23 2019 (r351029) @@ -111,7 +111,7 @@ cpu_fork(struct thread *td1, struct proc *p2, struct t /* Setup to release spin count in fork_exit(). */ td2->td_md.md_spinlock_count = 1; - td2->td_md.md_saved_daif = 0; + td2->td_md.md_saved_daif = td1->td_md.md_saved_daif & ~DAIF_I_MASKED; } void @@ -182,7 +182,7 @@ cpu_copy_thread(struct thread *td, struct thread *td0) /* Setup to release spin count in fork_exit(). */ td->td_md.md_spinlock_count = 1; - td->td_md.md_saved_daif = 0; + td->td_md.md_saved_daif = td0->td_md.md_saved_daif & ~DAIF_I_MASKED; } /* Modified: stable/12/sys/arm64/include/armreg.h ============================================================================== --- stable/12/sys/arm64/include/armreg.h Wed Aug 14 16:12:03 2019 (r351028) +++ stable/12/sys/arm64/include/armreg.h Wed Aug 14 16:40:23 2019 (r351029) @@ -66,6 +66,12 @@ #define CTR_ILINE_MASK (0xf << CTR_ILINE_SHIFT) #define CTR_ILINE_SIZE(reg) (((reg) & CTR_ILINE_MASK) >> CTR_ILINE_SHIFT) +/* DAIF - Interrupt Mask Bits */ +#define DAIF_D_MASKED (1 << 9) +#define DAIF_A_MASKED (1 << 8) +#define DAIF_I_MASKED (1 << 7) +#define DAIF_F_MASKED (1 << 6) + /* DCZID_EL0 - Data Cache Zero ID register */ #define DCZID_DZP (1 << 4) /* DC ZVA prohibited if non-0 */ #define DCZID_BS_SHIFT 0