From owner-freebsd-current  Mon Mar 25 09:28:49 1996
Return-Path: owner-current
Received: (from root@localhost)
          by freefall.freebsd.org (8.7.3/8.7.3) id JAA14492
          for current-outgoing; Mon, 25 Mar 1996 09:28:49 -0800 (PST)
Received: from phaeton.artisoft.com (phaeton.Artisoft.COM [198.17.250.211])
          by freefall.freebsd.org (8.7.3/8.7.3) with SMTP id JAA14484
          Mon, 25 Mar 1996 09:28:45 -0800 (PST)
Received: (from terry@localhost) by phaeton.artisoft.com (8.6.11/8.6.9) id KAA12203; Mon, 25 Mar 1996 10:18:05 -0700
From: Terry Lambert <terry@lambert.org>
Message-Id: <199603251718.KAA12203@phaeton.artisoft.com>
Subject: Re: Crash advice needed APPENDIX B
To: rgrimes@GndRsh.aac.dev.com (Rodney W. Grimes)
Date: Mon, 25 Mar 1996 10:18:04 -0700 (MST)
Cc: cau@cc.gatech.edu, uhclem@nemesis.lonestar.org, hackers@FreeBSD.ORG,
        current@FreeBSD.ORG
In-Reply-To: <199603250516.VAA28302@GndRsh.aac.dev.com> from "Rodney W. Grimes" at Mar 24, 96 09:16:47 pm
X-Mailer: ELM [version 2.4 PL24]
MIME-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: 7bit
Sender: owner-current@FreeBSD.ORG
X-Loop: FreeBSD.org
Precedence: bulk

> > > Because SCO Unix, Windows 95 and Windows NT are all gross in the way
> > > they handled bus master DMA disk controllers, they use a dedicated
> > > buffer area that is marked uncacheable just so they can run on the
> > > broken cache coherency motherboards.    Can you say totally defeat
> > > the purpose of bus master DMA buy having the processor bcopy data
> > > around...
> > 
> > Unfortunately, I've got one of these broken motherboards.  Is
> > there a way to make FreeBSD behave the same way?  That is, to
> > mark some memory block uncacheable (I guess this would be the
> > bounce buffers area)?  I realize this would be counterproductive
> > (decreased performance) in most cases, but in my case it might
> > help (I am able to use my DMA busmaster car at lower CPU
> > speeds, but I'd like to see the results of using a higher clock
> > value).
> 
> I can only theorize here as I am not that familiar with the current
> vm system in FreeBSD but... it should not be that major of a task
> to mark the bounce buffer region as uncachable (simply 1 or 2 bits
> per PTE in the page tables for this region) and then modify the
> bounce buffer code to _always_ bounce the I/O through the buffer.
> 
> This would totally defeat bus mastered DMA, but it would infact allow
> broken hardware to run.

I'd like to point out at this time that Cyrix/TI chipmask processors
not based on the IBM masks Cyrix got a while back do *not* honor the
non-cacheable bit in any case.

A BINVD would be required to manually flush the cache, or the cache
would still need to be turned off for these systems.


					Terry Lambert
					terry@lambert.org
---
Any opinions in this posting are my own and not those of my present
or previous employers.