From owner-freebsd-wireless@FreeBSD.ORG Thu Jan 8 05:10:24 2015 Return-Path: Delivered-To: wireless@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 27EBE3E4 for ; Thu, 8 Jan 2015 05:10:24 +0000 (UTC) Received: from nm19-vm2.access.bullet.mail.bf1.yahoo.com (nm19-vm2.access.bullet.mail.bf1.yahoo.com [216.109.115.97]) (using TLSv1 with cipher ECDHE-RSA-RC4-SHA (128/128 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id CBDB877A for ; Thu, 8 Jan 2015 05:10:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=att.net; s=s1024; t=1420693816; bh=bj4pisAi2CJis/3MP5X+U92MZCGqOR+YepdOOu+3xaM=; h=Date:From:To:CC:Subject:References:In-Reply-To:From:Subject; b=oVJa5EtsXkZOBcAkC92FdL7dGpR9mqUgyf1OOPaP7sZBEmL1gnebkwZvDZcgRTg6TVGltgQZV8Ya20Q9BzBJN0PiD3E28Iyom+4Mq78naYPOl0MXDqLWOM+GMnk6Puzduqlm6EjW1wd0jI6CgEt59emqOnyAJMsiGjrzj8j1NqA= DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=s1024; d=att.net; b=D011ImVSj+riVogKH/8ERvpW7EgwdO7k0IwLAARRSVyYuADdgD0J1dpDajFcPOfOdPos6NLtzDRyZJuCTSyAKI3JX8PTlnlIXY/QgecKWQT5wyJPk6j+55dKpXWH1tcgjCtNttHIZONKO0KMAonbtZaNtm9HKYtFHJ39qOfvlhg=; Received: from [66.196.81.155] by nm19.access.bullet.mail.bf1.yahoo.com with NNFMP; 08 Jan 2015 05:10:16 -0000 Received: from [98.138.226.240] by tm1.access.bullet.mail.bf1.yahoo.com with NNFMP; 08 Jan 2015 05:10:16 -0000 Received: from [127.0.0.1] by smtp111.sbc.mail.ne1.yahoo.com with NNFMP; 08 Jan 2015 05:10:16 -0000 X-Yahoo-Newman-Id: 56107.72020.bm@smtp111.sbc.mail.ne1.yahoo.com X-Yahoo-Newman-Property: ymail-3 X-YMail-OSG: tdPabIQVM1n1Y0DeaE_d6MgWIDlUfsRSHX.kS17xI1qYeJt 2trowj1yXw47jTST0p0K.v4eCf4jen7dWAnMmMYtpf1_S96ydhiwG1Z_MKCe gBfPM3uemXkaDOZEZPQdg5LJwxt2.0F4riytZI4j3XoYu87BAlfnPNz6r0c5 imlHZLxyqJDk9nwE5Dx0L1VTk1EgNNK_3c3bSjuO40bSuxbzNg4Lsspi7h1B rMruL_iiqjg0I6qHvRF9c5uQOd27wPdmo42E0_LSHW_BOVcyV1UTrk.L4zzX 1RR9iPEJx8SHfxNVOe0yE9tLm9UBqhWLhwNGVqRYNljj_A6hNnVS2lEzZ2Jy qBxCzoP.MIqRrgaBuAThkVg_TTgLRoS.t8X0rWW1K1B6nBngQRO2w_EoWBYT CxCnQwkuv7WcWKGpTid5RNkNvRvKOWNmDyTvnrs_zPPlDAYxHJIf3CfuFegi Oqxwa3X5V.hfzo6olhJDMdr9egk5FZs9YtMBAIq5cV7RkjqoFHsVy.xnoQS1 xfXLgGkDnBL_P60k1Cn3b38iLjTyTEoH8xAJwUop6mXy_.XdO X-Yahoo-SMTP: OKD1keCswBBTAmAF1s00hLyKW3wE3YfSK0Eazl6b4VZG4LTqJxg- Message-ID: <54AE1136.8000706@att.net> Date: Thu, 08 Jan 2015 00:10:14 -0500 From: Anthony Jenkins User-Agent: Mozilla/5.0 (X11; FreeBSD amd64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: Adrian Chadd Subject: Re: Atheros AR9565 detected, not working References: <433678684.160603.1419257025708.JavaMail.yahoo@jws10658.mail.bf1.yahoo.com> <54987366.6060803@yahoo.com> <5498780B.90704@yahoo.com> <5498944C.4040706@yahoo.com> <54AD3DF5.1070905@att.net> In-Reply-To: <54AD3DF5.1070905@att.net> Content-Type: multipart/mixed; boundary="------------060205090006000908000504" Cc: Anthony Jenkins , "wireless@freebsd.org" X-BeenThere: freebsd-wireless@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: "Discussions of 802.11 stack, tools device driver development." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 08 Jan 2015 05:10:24 -0000 This is a multi-part message in MIME format. --------------060205090006000908000504 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Removing just the ar9300_enable_rf_kill() bit works too, but now ath(4) endlessly spews ath0: ath_edma_rxfifo_alloc: Q1: alloc failed: i=3, nbufs=128? ath0: ath_edma_rxbuf_alloc: nothing on rxbuf?! ath0: ath_edma_rxfifo_alloc: Q1: alloc failed: i=0, nbufs=128? ath0: ath_edma_rxbuf_alloc: nothing on rxbuf?! ath0: ath_edma_rxfifo_alloc: Q1: alloc failed: i=1, nbufs=128? ath0: ath_edma_rxbuf_alloc: nothing on rxbuf?! ath0: ath_edma_rxfifo_alloc: Q1: alloc failed: i=0, nbufs=128? ath0: ath_edma_rxbuf_alloc: nothing on rxbuf?! ath0: ath_edma_rxfifo_alloc: Q1: alloc failed: i=2, nbufs=128? ath0: ath_edma_rxbuf_alloc: nothing on rxbuf?! ath0: ath_edma_rxfifo_alloc: Q1: alloc failed: i=0, nbufs=128? ath0: ath_edma_rxbuf_alloc: nothing on rxbuf?! ath0: ath_edma_rxfifo_alloc: Q1: alloc failed: i=1, nbufs=128? ath0: ath_edma_rxbuf_alloc: nothing on rxbuf?! ath0: ath_edma_rxfifo_alloc: Q1: alloc failed: i=0, nbufs=128? ath0: ath_edma_rxbuf_alloc: nothing on rxbuf?! ath0: ath_edma_rxfifo_alloc: Q1: alloc failed: i=2, nbufs=128? ath0: ath_edma_rxbuf_alloc: nothing on rxbuf?! ath0: ath_edma_rxfifo_alloc: Q1: alloc failed: i=0, nbufs=128? Also changed GPIO patch to not block/just/ pin 11 ops instead of all pins as in previous patch, but if allowing all pins is kosher I'd prefer that. Anthony On 01/07/2015 09:08, Anthony Jenkins wrote: > Hi Adrian, > > Just letting you know I haven't died in a shootout with the US FBI or anything, just been working on (and suprisingly fixing) issues with my HP Envy Sleekbook 6 since the holidays. I'll be cleaning up my patches and posting to the wiki this week (hopefully). Also still sitting on that ACPI patch for the RTC CMOS handler. > >> So, would you mind trying your patch again but only with the bits that >> allow the GPIO pins to be enabled? If that works, then I'll commit >> that > Just to be clear, instead of commenting out the early exits in the GPIO readers/writers for certain GPIO addresses, I should selectively give the AR9565 a pass? ...or do you want me to /just/ comment out the early exits, and revert the added call to ar9300_enable_rf_kill() and see if that works? I don't like those early exit bits anyway... >> In parallel I'm going to have to tidy up the rfkill capability >> API to correctly set bits - I'll likely expand the field in the driver >> and have the pre-AR9300 chipset code error out if an out-of-bounds >> gpio value is sent. > Excellent! Anything I can help with? We /have/ an rfkill API? ...because I need some way to connect my newly-fixed laptop wifi-enable key to some function to enable/disable the radios. Right now I'm just throwing an event over to devd(8). > > Thanks, > Anthony > > On 12/23/2014 13:06, Adrian Chadd wrote: >> On 22 December 2014 at 14:57, Adrian Chadd wrote: >> >>> Ok, let me go see what's going on. >> I dislike when I say "let me see what's going on" and then I .. see >> what's going on. >> >> So: >> >> * the ar5212 HAL does the right thing - it checks the rfkill setup in >> ar5212Reset() and enables it if required >> * it also populates the rfkill data from EEPROM at attach time >> * the sysctl code just grabs the rfkill /eeprom field/ and .. well, >> that's the API. So I have to see if that's the same for the AR9300 or >> not. Grr. >> >> Well, it kinda is: >> >> ar9300eep.h:#define EEP_RFSILENT_ENABLED 0x0001 /* bit 0: >> enabled/disabled */ >> ar9300eep.h:#define EEP_RFSILENT_ENABLED_S 0 /* bit 0: >> enabled/disabled */ >> ar9300eep.h:#define EEP_RFSILENT_POLARITY 0x0002 /* bit 1: polarity */ >> ar9300eep.h:#define EEP_RFSILENT_POLARITY_S 1 /* bit 1: polarity */ >> ar9300eep.h:#define EEP_RFSILENT_GPIO_SEL 0x00fc /* bits 2..7: >> gpio PIN */ >> ar9300eep.h:#define EEP_RFSILENT_GPIO_SEL_S 2 /* bits 2..7: >> gpio PIN */ >> >> .. but on the AR5212: >> >> ../ah_eeprom_v1.h:#define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c >> ../ah_eeprom_v1.h:#define AR_EEPROM_RFSILENT_GPIO_SEL_S 2 >> ../ah_eeprom_v1.h:#define AR_EEPROM_RFSILENT_POLARITY 0x0002 >> ../ah_eeprom_v1.h:#define AR_EEPROM_RFSILENT_POLARITY_S 1 >> ../ah_eeprom_v3.h:#define AR_EEPROM_RFSILENT 0x0f /* RF >> Silent/Clock Run Enable */ >> ../ah_eeprom_v3.h:#define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c >> ../ah_eeprom_v3.h:#define AR_EEPROM_RFSILENT_GPIO_SEL_S 2 >> ../ah_eeprom_v3.h:#define AR_EEPROM_RFSILENT_POLARITY 0x0002 >> ../ah_eeprom_v3.h:#define AR_EEPROM_RFSILENT_POLARITY_S 1 >> >> .. so more bits are available on the ar9300. I have to check the >> AR5416 too; maybe more bits are also available there. >> >> Grr! >> >> * Then, the Ar5212 is doing it in ar5212Reset(), but ar5416Reset() >> isn't doing it! So I'm going to have to go and hook that up for the >> AR5416, AR9160, AR9280, AR9285, AR9287. Ugh. >> >> * the ar9300 HAL on -HEAD has this in ar9300_reset(): >> >> /* Reset ier reference count to disabled */ >> // OS_ATOMIC_SET(&ahp->ah_ier_ref_count, 1);C >> if (ath_hal_isrfkillenabled(ah)) { >> ar9300_enable_rf_kill(ah); >> } >> >> .. so it should be enabling it at reset. We shouldn't need to enable >> it during ar9300_attach() as the first reset will set it up. >> >> * The AR5212 HAL enables rfkill interrupts, but the AR9300 doesn't. >> Apparently there are .. issues. I don't know what they are. So maybe >> we should use polling on that particular GPIO pin to provide rfkill >> feedback to the driver and eventually the network stack. >> >> So, would you mind trying your patch again but only with the bits that >> allow the GPIO pins to be enabled? If that works, then I'll commit >> that. In parallel I'm going to have to tidy up the rfkill capability >> API to correctly set bits - I'll likely expand the field in the driver >> and have the pre-AR9300 chipset code error out if an out-of-bounds >> gpio value is sent. >> >> Thanks! >> >> >> >> -adrian >> _______________________________________________ >> freebsd-wireless@freebsd.org mailing list >> http://lists.freebsd.org/mailman/listinfo/freebsd-wireless >> To unsubscribe, send any mail to "freebsd-wireless-unsubscribe@freebsd.org" >> --------------060205090006000908000504 Content-Type: text/x-patch; name="ath_ar9565_rfkill_gpio-2.0.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="ath_ar9565_rfkill_gpio-2.0.patch" Index: sys/contrib/dev/ath/ath_hal/ar9300/ar9300_gpio.c =================================================================== --- sys/contrib/dev/ath/ath_hal/ar9300/ar9300_gpio.c (revision 276098) +++ sys/contrib/dev/ath/ath_hal/ar9300/ar9300_gpio.c (working copy) @@ -161,10 +161,11 @@ }; HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins); - if ((gpio == AR9382_GPIO_PIN_8_RESERVED) || - (gpio == AR9382_GPIO_PIN_11_RESERVED) || + if ((gpio == AR9382_GPIO_PIN_8_RESERVED) /* || + (gpio == AR9382_GPIO_PIN_11_RESERVED) */ || (gpio == AR9382_GPIO_9_INPUT_ONLY)) { + ath_hal_printf(ah, "%s: Invalid GPIO 0x%x\n", __func__, gpio); return AH_FALSE; } @@ -347,10 +348,11 @@ u_int32_t gpio_shift; HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins); - if ((gpio == AR9382_GPIO_PIN_8_RESERVED) || - (gpio == AR9382_GPIO_PIN_11_RESERVED) || + if ((gpio == AR9382_GPIO_PIN_8_RESERVED) /* || + (gpio == AR9382_GPIO_PIN_11_RESERVED) */ || (gpio > AR9382_MAX_GPIO_INPUT_PIN_NUM)) { + ath_hal_printf(ah, "%s: Invalid GPIO 0x%x\n", __func__, gpio); return AH_FALSE; } @@ -377,12 +379,14 @@ ar9300_gpio_set(struct ath_hal *ah, u_int32_t gpio, u_int32_t val) { HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins); - if ((gpio == AR9382_GPIO_PIN_8_RESERVED) || - (gpio == AR9382_GPIO_PIN_11_RESERVED) || + if ((gpio == AR9382_GPIO_PIN_8_RESERVED) /* || + (gpio == AR9382_GPIO_PIN_11_RESERVED) */ || (gpio == AR9382_GPIO_9_INPUT_ONLY)) { + ath_hal_printf(ah, "%s: Invalid GPIO 0x%x\n", __func__, gpio); return AH_FALSE; } + ath_hal_printf(ah, "%s: GPIO 0x%x => %u\n", __func__, gpio, val); OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_OUT), ((val & 1) << gpio), AR_GPIO_BIT(gpio)); @@ -397,9 +401,10 @@ { u_int32_t gpio_in; HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins); - if ((gpio == AR9382_GPIO_PIN_8_RESERVED) || - (gpio == AR9382_GPIO_PIN_11_RESERVED)) + if (gpio == AR9382_GPIO_PIN_8_RESERVED /* || + gpio == AR9382_GPIO_PIN_11_RESERVED*/) { + ath_hal_printf(ah, "%s: Invalid GPIO 0x%x\n", __func__, gpio); return 0xffffffff; } @@ -452,10 +457,11 @@ HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins); - if ((gpio == AR9382_GPIO_PIN_8_RESERVED) || - (gpio == AR9382_GPIO_PIN_11_RESERVED) || + if ((gpio == AR9382_GPIO_PIN_8_RESERVED) /* || + (gpio == AR9382_GPIO_PIN_11_RESERVED) */ || (gpio > AR9382_MAX_GPIO_INPUT_PIN_NUM)) { + ath_hal_printf(ah, "%s: Invalid GPIO 0x%x\n", __func__, gpio); return; } @@ -549,8 +555,8 @@ if (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_AR9380_PCIE) { mask = (1 << AR9382_MAX_GPIO_PIN_NUM) - 1; - mask &= ~(1 << AR9382_GPIO_PIN_8_RESERVED | - 1 << AR9382_GPIO_PIN_11_RESERVED); + mask &= ~(1 << AR9382_GPIO_PIN_8_RESERVED /* | + 1 << AR9382_GPIO_PIN_11_RESERVED*/); } return mask; } @@ -562,8 +568,8 @@ if (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_AR9380_PCIE) { invalid = ~((1 << AR9382_MAX_GPIO_PIN_NUM) - 1); - invalid |= 1 << AR9382_GPIO_PIN_8_RESERVED | - 1 << AR9382_GPIO_PIN_11_RESERVED; + invalid |= 1 << AR9382_GPIO_PIN_8_RESERVED /* | + 1 << AR9382_GPIO_PIN_11_RESERVED*/; } if (mask & invalid) { ath_hal_printf(ah, "%s: invalid GPIO mask 0x%x\n", __func__, mask); --------------060205090006000908000504--