From owner-freebsd-mips@FreeBSD.ORG Fri Jul 15 16:09:53 2011 Return-Path: Delivered-To: freebsd-mips@FreeBSD.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id F16C4106566C; Fri, 15 Jul 2011 16:09:53 +0000 (UTC) (envelope-from imp@bsdimp.com) Received: from harmony.bsdimp.com (bsdimp.com [199.45.160.85]) by mx1.freebsd.org (Postfix) with ESMTP id ACCF18FC14; Fri, 15 Jul 2011 16:09:53 +0000 (UTC) Received: from [10.30.101.53] ([209.117.142.2]) (authenticated bits=0) by harmony.bsdimp.com (8.14.4/8.14.3) with ESMTP id p6FG4RKk030260 (version=TLSv1/SSLv3 cipher=DHE-DSS-AES128-SHA bits=128 verify=NO); Fri, 15 Jul 2011 10:04:28 -0600 (MDT) (envelope-from imp@bsdimp.com) Mime-Version: 1.0 (Apple Message framework v1084) Content-Type: text/plain; charset=us-ascii From: Warner Losh In-Reply-To: Date: Fri, 15 Jul 2011 10:02:59 -0600 Content-Transfer-Encoding: quoted-printable Message-Id: <023BB8FE-D486-4D3C-80F3-642BEB8FD72C@bsdimp.com> References: To: Adrian Chadd X-Mailer: Apple Mail (2.1084) X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.0.1 (harmony.bsdimp.com [10.0.0.6]); Fri, 15 Jul 2011 10:04:28 -0600 (MDT) Cc: freebsd-mips@FreeBSD.org Subject: Re: [PATCH] Fix initialization of i8259 controller on MALTA X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 15 Jul 2011 16:09:54 -0000 On Jul 15, 2011, at 4:08 AM, Adrian Chadd wrote: > The obvious question - is QEMU correct here? >=20 > Has anyone tried this on a real board? I'm not sure this has booted on a real board in a long time. Not = because it is broken, but because the MALTA boards are kinda old. Warner >=20 > Adrian >=20 > On 15 July 2011 08:16, Robert Millan wrote: >> Hi, >>=20 >> i8259 controller is initialized incorrectly on MALTA. It writes mask >> bits to control register and control bits to mask register. >>=20 >> The former causes ICW1_RESET|ICW1_LTIM combination to be written to >> control register, which on QEMU results in "level sensitive irq not >> supported" error. >>=20 >> -- >> Robert Millan >>=20 >> _______________________________________________ >> freebsd-mips@freebsd.org mailing list >> http://lists.freebsd.org/mailman/listinfo/freebsd-mips >> To unsubscribe, send any mail to = "freebsd-mips-unsubscribe@freebsd.org" >>=20 >>=20 > _______________________________________________ > freebsd-mips@freebsd.org mailing list > http://lists.freebsd.org/mailman/listinfo/freebsd-mips > To unsubscribe, send any mail to = "freebsd-mips-unsubscribe@freebsd.org" >=20 >=20