From owner-svn-src-head@FreeBSD.ORG Thu Apr 30 19:23:52 2015 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 1ED08899; Thu, 30 Apr 2015 19:23:52 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 0D58511E9; Thu, 30 Apr 2015 19:23:52 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.9/8.14.9) with ESMTP id t3UJNppb002777; Thu, 30 Apr 2015 19:23:51 GMT (envelope-from neel@FreeBSD.org) Received: (from neel@localhost) by svn.freebsd.org (8.14.9/8.14.9/Submit) id t3UJNpcl002774; Thu, 30 Apr 2015 19:23:51 GMT (envelope-from neel@FreeBSD.org) Message-Id: <201504301923.t3UJNpcl002774@svn.freebsd.org> X-Authentication-Warning: svn.freebsd.org: neel set sender to neel@FreeBSD.org using -f From: Neel Natu Date: Thu, 30 Apr 2015 19:23:51 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r282281 - in head/sys/amd64/vmm: . amd intel X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 30 Apr 2015 19:23:52 -0000 Author: neel Date: Thu Apr 30 19:23:50 2015 New Revision: 282281 URL: https://svnweb.freebsd.org/changeset/base/282281 Log: Advertise the MTRR feature via CPUID and emulate the minimal set of MTRR MSRs. This is required for booting Windows guests. Reported by: Leon Dang (ldang@nahannisys.com) MFC after: 2 weeks Modified: head/sys/amd64/vmm/amd/svm_msr.c head/sys/amd64/vmm/intel/vmx_msr.c head/sys/amd64/vmm/x86.c Modified: head/sys/amd64/vmm/amd/svm_msr.c ============================================================================== --- head/sys/amd64/vmm/amd/svm_msr.c Thu Apr 30 18:23:38 2015 (r282280) +++ head/sys/amd64/vmm/amd/svm_msr.c Thu Apr 30 19:23:50 2015 (r282281) @@ -27,12 +27,18 @@ #include __FBSDID("$FreeBSD$"); -#include +#include #include +#include +#include #include #include +#include +#include "svm.h" +#include "vmcb.h" +#include "svm_softc.h" #include "svm_msr.h" #ifndef MSR_AMDK8_IPM @@ -105,6 +111,13 @@ svm_rdmsr(struct svm_softc *sc, int vcpu int error = 0; switch (num) { + case MSR_MTRRcap: + case MSR_MTRRdefType: + case MSR_MTRR4kBase ... MSR_MTRR4kBase + 8: + case MSR_MTRR16kBase ... MSR_MTRR16kBase + 1: + case MSR_MTRR64kBase: + *result = 0; + break; case MSR_AMDK8_IPM: *result = 0; break; @@ -122,6 +135,14 @@ svm_wrmsr(struct svm_softc *sc, int vcpu int error = 0; switch (num) { + case MSR_MTRRcap: + vm_inject_gp(sc->vm, vcpu); + break; + case MSR_MTRRdefType: + case MSR_MTRR4kBase ... MSR_MTRR4kBase + 8: + case MSR_MTRR16kBase ... MSR_MTRR16kBase + 1: + case MSR_MTRR64kBase: + break; /* Ignore writes */ case MSR_AMDK8_IPM: /* * Ignore writes to the "Interrupt Pending Message" MSR. Modified: head/sys/amd64/vmm/intel/vmx_msr.c ============================================================================== --- head/sys/amd64/vmm/intel/vmx_msr.c Thu Apr 30 18:23:38 2015 (r282280) +++ head/sys/amd64/vmm/intel/vmx_msr.c Thu Apr 30 19:23:50 2015 (r282281) @@ -396,6 +396,13 @@ vmx_rdmsr(struct vmx *vmx, int vcpuid, u error = 0; switch (num) { + case MSR_MTRRcap: + case MSR_MTRRdefType: + case MSR_MTRR4kBase ... MSR_MTRR4kBase + 8: + case MSR_MTRR16kBase ... MSR_MTRR16kBase + 1: + case MSR_MTRR64kBase: + *val = 0; + break; case MSR_IA32_MISC_ENABLE: *val = misc_enable; break; @@ -427,6 +434,14 @@ vmx_wrmsr(struct vmx *vmx, int vcpuid, u error = 0; switch (num) { + case MSR_MTRRcap: + vm_inject_gp(vmx->vm, vcpuid); + break; + case MSR_MTRRdefType: + case MSR_MTRR4kBase ... MSR_MTRR4kBase + 8: + case MSR_MTRR16kBase ... MSR_MTRR16kBase + 1: + case MSR_MTRR64kBase: + break; /* Ignore writes */ case MSR_IA32_MISC_ENABLE: changed = val ^ misc_enable; /* Modified: head/sys/amd64/vmm/x86.c ============================================================================== --- head/sys/amd64/vmm/x86.c Thu Apr 30 18:23:38 2015 (r282280) +++ head/sys/amd64/vmm/x86.c Thu Apr 30 19:23:50 2015 (r282281) @@ -289,9 +289,8 @@ x86_emulate_cpuid(struct vm *vm, int vcp /* * Machine check handling is done in the host. - * Hide MTRR capability. */ - regs[3] &= ~(CPUID_MCA | CPUID_MCE | CPUID_MTRR); + regs[3] &= ~(CPUID_MCA | CPUID_MCE); /* * Hide the debug store capability.