From owner-cvs-src Sat Feb 15 11:21:45 2003 Delivered-To: cvs-src@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 6E7F437B401; Sat, 15 Feb 2003 11:21:43 -0800 (PST) Received: from canning.wemm.org (canning.wemm.org [192.203.228.65]) by mx1.FreeBSD.org (Postfix) with ESMTP id 0BB8C43F3F; Sat, 15 Feb 2003 11:21:43 -0800 (PST) (envelope-from peter@wemm.org) Received: from wemm.org (localhost [127.0.0.1]) by canning.wemm.org (Postfix) with ESMTP id E79BE2A89E; Sat, 15 Feb 2003 11:21:42 -0800 (PST) (envelope-from peter@wemm.org) X-Mailer: exmh version 2.5 07/13/2001 with nmh-1.0.4 To: Marcel Moolenaar Cc: Eric Anholt , src-committers@FreeBSD.org, cvs-src@FreeBSD.org, cvs-all@FreeBSD.org Subject: Re: cvs commit: src/sys/modules Makefile In-Reply-To: <20030214061708.GA2109@athlon.pn.xcllnt.net> Date: Sat, 15 Feb 2003 11:21:42 -0800 From: Peter Wemm Message-Id: <20030215192142.E79BE2A89E@canning.wemm.org> Sender: owner-cvs-src@FreeBSD.ORG Precedence: bulk List-ID: List-Archive: (Web Archive) List-Help: (List Instructions) List-Subscribe: List-Unsubscribe: X-Loop: FreeBSD.ORG Marcel Moolenaar wrote: > On Thu, Feb 13, 2003 at 09:32:33PM -0800, Eric Anholt wrote: > > > > > > In that case, we'd better make sure there's cache coherency. Do we > > > actually have the code structured in a way that allows having the > > > flushing chipset dependent (not to mention dependent on the address)? > > > > No, currently all the cache flushes (four in agp.c, three in i810 and > > amd code) are unconditional agp_flush_cache calls after modifying the > > gatt entries. They aren't tied to a specific memory range, but could be > > pretty easily, if not the most efficiently, by pushing some of them into > > the (un)bind_pages. There's probably a better way. > > I wonder: do we actually need to flush at all? GART updates are PCI/AGP > writes and should be coherent, right? Consider the remap table. It is external to the cpu, on the far side of the writeback cache. Changing remap entries with pending writes would be interesting. AGP isn't necessarily coherent either. > Also, on ia64 bus I/O is done with a virtual address that has the > non-cacheable property. Flushing would not be required irrespective. What about user mmaped IO? eg: when the Xserver has got stuff remapped down into user memory? And what if the remap table is changed underneath that? On i386, the MTRR stuff is used to control cache behavior so that the userland portions can be in writeback mode. I dont recall what happens on ia64. I really dont understand this stuff well enough. Cheers, -Peter -- Peter Wemm - peter@wemm.org; peter@FreeBSD.org; peter@yahoo-inc.com "All of this is for nothing if we don't go to the stars" - JMS/B5 To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe cvs-src" in the body of the message