From owner-svn-src-all@freebsd.org Wed Dec 5 13:45:10 2018 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 1391D1313F41; Wed, 5 Dec 2018 13:45:10 +0000 (UTC) (envelope-from slavash@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id AB7B47270D; Wed, 5 Dec 2018 13:45:09 +0000 (UTC) (envelope-from slavash@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 8C9A615293; Wed, 5 Dec 2018 13:45:09 +0000 (UTC) (envelope-from slavash@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id wB5Dj9rh081646; Wed, 5 Dec 2018 13:45:09 GMT (envelope-from slavash@FreeBSD.org) Received: (from slavash@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id wB5Dj9wO081644; Wed, 5 Dec 2018 13:45:09 GMT (envelope-from slavash@FreeBSD.org) Message-Id: <201812051345.wB5Dj9wO081644@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: slavash set sender to slavash@FreeBSD.org using -f From: Slava Shwartsman Date: Wed, 5 Dec 2018 13:45:09 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r341563 - in head/sys/dev/mlx5: . mlx5_core X-SVN-Group: head X-SVN-Commit-Author: slavash X-SVN-Commit-Paths: in head/sys/dev/mlx5: . mlx5_core X-SVN-Commit-Revision: 341563 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: AB7B47270D X-Spamd-Result: default: False [-0.62 / 15.00]; local_wl_from(0.00)[FreeBSD.org]; NEURAL_HAM_MEDIUM(-0.52)[-0.521,0]; NEURAL_HAM_SHORT(-0.07)[-0.070,0]; NEURAL_HAM_LONG(-0.03)[-0.031,0]; ASN(0.00)[asn:11403, ipnet:2610:1c1:1::/48, country:US] X-Rspamd-Server: mx1.freebsd.org X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 05 Dec 2018 13:45:10 -0000 Author: slavash Date: Wed Dec 5 13:45:08 2018 New Revision: 341563 URL: https://svnweb.freebsd.org/changeset/base/341563 Log: mlx5: Implement support for configuring PCIe packet write ordering via a sysctl. Submitted by: hselasky@ Approved by: hselasky (mentor) MFC after: 1 week Sponsored by: Mellanox Technologies Modified: head/sys/dev/mlx5/mlx5_core/mlx5_mr.c head/sys/dev/mlx5/mlx5_ifc.h Modified: head/sys/dev/mlx5/mlx5_core/mlx5_mr.c ============================================================================== --- head/sys/dev/mlx5/mlx5_core/mlx5_mr.c Wed Dec 5 13:44:38 2018 (r341562) +++ head/sys/dev/mlx5/mlx5_core/mlx5_mr.c Wed Dec 5 13:45:08 2018 (r341563) @@ -1,5 +1,5 @@ /*- - * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. + * Copyright (c) 2013-2018, Mellanox Technologies, Ltd. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -30,6 +30,11 @@ #include #include "mlx5_core.h" +static int mlx5_relaxed_ordering_write; +SYSCTL_INT(_hw_mlx5, OID_AUTO, relaxed_ordering_write, CTLFLAG_RWTUN, + &mlx5_relaxed_ordering_write, 0, + "Set to enable relaxed ordering for PCIe writes"); + void mlx5_init_mr_table(struct mlx5_core_dev *dev) { struct mlx5_mr_table *table = &dev->priv.mr_table; @@ -63,6 +68,14 @@ int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry); MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY); MLX5_SET(mkc, mkc, mkey_7_0, key); + + if (mlx5_relaxed_ordering_write != 0) { + if (MLX5_CAP_GEN(dev, relaxed_ordering_write)) + MLX5_SET(mkc, mkc, relaxed_ordering_write, 1); + else + return (-EPROTONOSUPPORT); + } + if (callback) return mlx5_cmd_exec_cb(dev, in, inlen, out, outlen, callback, context); Modified: head/sys/dev/mlx5/mlx5_ifc.h ============================================================================== --- head/sys/dev/mlx5/mlx5_ifc.h Wed Dec 5 13:44:38 2018 (r341562) +++ head/sys/dev/mlx5/mlx5_ifc.h Wed Dec 5 13:45:08 2018 (r341563) @@ -933,7 +933,8 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 log_max_cq[0x5]; u8 log_max_eq_sz[0x8]; - u8 reserved_6[0x2]; + u8 relaxed_ordering_write[1]; + u8 reserved_6[0x1]; u8 log_max_mkey[0x6]; u8 reserved_7[0xc]; u8 log_max_eq[0x4]; @@ -2424,9 +2425,13 @@ enum { }; struct mlx5_ifc_mkc_bits { - u8 reserved_0[0x1]; + u8 reserved_at_0[0x1]; u8 free[0x1]; - u8 reserved_1[0xd]; + u8 reserved_at_2[0x1]; + u8 access_mode_4_2[0x3]; + u8 reserved_at_6[0x7]; + u8 relaxed_ordering_write[0x1]; + u8 reserved_at_e[0x1]; u8 small_fence_on_rdma_read_response[0x1]; u8 umr_en[0x1]; u8 a[0x1];