From owner-freebsd-arm@freebsd.org Sun Dec 13 17:07:49 2020 Return-Path: Delivered-To: freebsd-arm@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id B7E8C4BDE73 for ; Sun, 13 Dec 2020 17:07:49 +0000 (UTC) (envelope-from manu@bidouilliste.com) Received: from mx.blih.net (mx.blih.net [212.83.155.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (2048 bits) client-digest SHA256) (Client CN "mx.blih.net", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4Cv9v92r5Qz4dly; Sun, 13 Dec 2020 17:07:48 +0000 (UTC) (envelope-from manu@bidouilliste.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bidouilliste.com; s=mx; t=1607879266; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=sG2CsCJglElF6PM+lirlqGq46SV6YFjcLT6X6T2ygAQ=; b=SiG9gXZeACZ4b4tld/xcixtCbdvb9WNcISSMnxNkRJFqpbZKYqxi8WFvKOSfLjYynYWEkp i9EDomxzdeupKWU+mXx/mwZlMcymZWfUjll21NBQG1SGSiivDQ6AFct1NZ/hDqPL3MdfNB fRZFM0v3tHuTPLJ0oYdUMipDIarjJp4= Received: from skull.home.blih.net (lfbn-idf2-1-288-247.w82-123.abo.wanadoo.fr [82.123.126.247]) by mx.blih.net (OpenSMTPD) with ESMTPSA id 160f2927 (TLSv1.3:TLS_AES_256_GCM_SHA384:256:NO); Sun, 13 Dec 2020 17:07:46 +0000 (UTC) Date: Sun, 13 Dec 2020 18:07:46 +0100 From: Emmanuel Vadot To: =?ISO-8859-1?Q?S=F8ren?= Schmidt Cc: Ian Lepore , freebsd-arm , Daniel Engberg Subject: Re: FreeBSD-13.0-CURRENT-arm64-aarch64-ROCKPRO64-20201210-7578a4862f0 broken ? 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List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 13 Dec 2020 17:07:49 -0000 On Sun, 13 Dec 2020 17:33:45 +0100 S=F8ren Schmidt wrote: >=20 >=20 > > On 13 Dec 2020, at 11.26, S=F8ren Schmidt wro= te: > >=20 > >> On 13 Dec 2020, at 00.00, Ian Lepore > wrote: > >>=20 > >> On Sat, 2020-12-12 at 23:53 +0100, Daniel Engberg wrote: > >>> Hi, > >>>=20 > >>> While I haven't tried the exact version you're referring to I have a= =20 > >>> slightly older image that I compiled myself and it runs fine. The > >>> only=20 > >>> difference I can tell is that the memory (RAM) seems to be configure= =20 > >>> different on your device. I can provide a copy of the image if you > >>> want. > >>>=20 > >>> U-Boot TPL 2020.10 (Dec 02 2020 - 23:00:31) > >>> Channel 0: LPDDR4, 50MHz > >>> BW=3D32 Col=3D10 Bk=3D8 CS0 Row=3D15 CS1 Row=3D15 CS=3D2 Die BW=3D16 = Size=3D2048MB > >>> Channel 1: LPDDR4, 50MHz > >>> BW=3D32 Col=3D10 Bk=3D8 CS0 Row=3D15 CS1 Row=3D15 CS=3D2 Die BW=3D16 = Size=3D2048MB > >>> 256B stride > >>> lpddr4_set_rate: change freq to 400000000 mhz 0, 1 > >>> lpddr4_set_rate: change freq to 800000000 mhz 1, 0 > >>> Trying to boot from BOOTROM > >>> Returning to boot ROM... > >>>=20 > >>=20 > >> That's interesting, because my first thought was "memory config > >> problem", due to the mod-after-free "error" actually appearing to be a > >> single-bit ram error (val=3Ddeadc0df vs deadc0de). > >>=20 > >> -- Ian > >=20 > >=20 > > Yes, something fishy is going on with the memory setup? > > From a working NetBSD boot: > >=20 > > channel 0 training pass! > > channel 1 training pass! > > change freq to 800MHz 1,0 > > Channel 0: LPDDR4,800MHz > > Bus Width=3D32 Col=3D10 Bank=3D8 Row=3D16 CS=3D1 Die Bus-Width=3D16 Siz= e=3D2048MB > > Channel 1: LPDDR4,800MHz > > Bus Width=3D32 Col=3D10 Bank=3D8 Row=3D16 CS=3D1 Die Bus-Width=3D16 Siz= e=3D2048MB > > 256B stride > > ch 0 ddrconfig =3D 0x101, ddrsize =3D 0x40 > > ch 1 ddrconfig =3D 0x101, ddrsize =3D 0x40 > >=20 >=20 > Just tried to use their u-boot image to boot -current, and that works fin= e. >=20 > So, our port of u-boot or the official one has something borked for this = combo since after 2019.10. >=20 > It is running a build world now on a NVMe stick, so lets see how that tur= ns out? (just 4 cores the big/litte thing is still not solved it seems).. >=20 > S=F8ren Schmidt > sos@deepcore.dk / sos@freebsd.org > "So much code to hack, so little time" So, I have two rockpro64 here. The first one was sent to me by Pine when they launched the product and the other one I received last month. Both are labeled as v2.1 but the first one was produced opn 2018-06-06 while the second one was on 2018-07-02 Both works great and boot 100% of the time. But there is indeed some difference in the dram setup. Boot for the 0606 one : U-Boot TPL 2020.10 (Dec 10 2020 - 10:13:59) Channel 0: LPDDR4, 50MHz BW=3D32 Col=3D10 Bk=3D8 CS0 Row=3D15 CS1 Row=3D15 CS=3D2 Die BW=3D16 Size= =3D2048MB Channel 1: LPDDR4, 50MHz BW=3D32 Col=3D10 Bk=3D8 CS0 Row=3D15 CS1 Row=3D15 CS=3D2 Die BW=3D16 Size= =3D2048MB 256B stride lpddr4_set_rate: change freq to 400000000 mhz 0, 1 lpddr4_set_rate: change freq to 800000000 mhz 1, 0 Boot for the 0702 one : U-Boot TPL 2020.10 (Dec 10 2020 - 10:13:59) Channel 0: LPDDR4, 50MHz BW=3D32 Col=3D10 Bk=3D8 CS0 Row=3D16/15 CS=3D1 Die BW=3D16 Size=3D2048MB Channel 1: LPDDR4, 50MHz BW=3D32 Col=3D10 Bk=3D8 CS0 Row=3D16/15 CS=3D1 Die BW=3D16 Size=3D2048MB 256B stride lpddr4_set_rate: change freq to 400000000 mhz 0, 1 lpddr4_set_rate: change freq to 800000000 mhz 1, 0 Our u-boot ports doesn't do anything weird so I don't think that your problem is related to this. There is a lot of debug info available in https://github.com/u-boot/u-boot/blob/master/drivers/ram/rockchip/sdram_rk3= 399.c so maybe try to compile with debug enabled and see if it logs anything useful ? --=20 Emmanuel Vadot