Date: Sun, 4 Feb 2018 20:07:09 +0000 (UTC) From: Justin Hibbits <jhibbits@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r328862 - head/sys/powerpc/mpc85xx Message-ID: <201802042007.w14K79aQ022675@repo.freebsd.org>
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Author: jhibbits Date: Sun Feb 4 20:07:08 2018 New Revision: 328862 URL: https://svnweb.freebsd.org/changeset/base/328862 Log: Only look for L2 cache controllers for mpc85xx_cache The L3 cache controller (Corenet Platform Cache) is listed with one of its compatible strings as "cache", which this driver can't attach to. Restrict to a known list of primary cache controller strings, as found in the l2cache devicetree binding. Modified: head/sys/powerpc/mpc85xx/mpc85xx_cache.c Modified: head/sys/powerpc/mpc85xx/mpc85xx_cache.c ============================================================================== --- head/sys/powerpc/mpc85xx/mpc85xx_cache.c Sun Feb 4 19:43:51 2018 (r328861) +++ head/sys/powerpc/mpc85xx/mpc85xx_cache.c Sun Feb 4 20:07:08 2018 (r328862) @@ -56,11 +56,53 @@ struct mpc85xx_cache_softc { struct resource *sc_mem; }; +static struct ofw_compat_data compats[] = { + {"fsl,8540-l2-cache-controller", 1}, + {"fsl,8541-l2-cache-controller", 1}, + {"fsl,8544-l2-cache-controller", 1}, + {"fsl,8548-l2-cache-controller", 1}, + {"fsl,8555-l2-cache-controller", 1}, + {"fsl,8568-l2-cache-controller", 1}, + {"fsl,b4420-l2-cache-controller", 1}, + {"fsl,b4860-l2-cache-controller", 1}, + {"fsl,bsc9131-l2-cache-controller", 1}, + {"fsl,bsc9132-l2-cache-controller", 1}, + {"fsl,c293-l2-cache-controller", 1}, + {"fsl,mpc8536-l2-cache-controller", 1}, + {"fsl,mpc8540-l2-cache-controller", 1}, + {"fsl,mpc8541-l2-cache-controller", 1}, + {"fsl,mpc8544-l2-cache-controller", 1}, + {"fsl,mpc8548-l2-cache-controller", 1}, + {"fsl,mpc8555-l2-cache-controller", 1}, + {"fsl,mpc8560-l2-cache-controller", 1}, + {"fsl,mpc8568-l2-cache-controller", 1}, + {"fsl,mpc8569-l2-cache-controller", 1}, + {"fsl,mpc8572-l2-cache-controller", 1}, + {"fsl,p1010-l2-cache-controller", 1}, + {"fsl,p1011-l2-cache-controller", 1}, + {"fsl,p1012-l2-cache-controller", 1}, + {"fsl,p1013-l2-cache-controller", 1}, + {"fsl,p1014-l2-cache-controller", 1}, + {"fsl,p1015-l2-cache-controller", 1}, + {"fsl,p1016-l2-cache-controller", 1}, + {"fsl,p1020-l2-cache-controller", 1}, + {"fsl,p1021-l2-cache-controller", 1}, + {"fsl,p1022-l2-cache-controller", 1}, + {"fsl,p1023-l2-cache-controller", 1}, + {"fsl,p1024-l2-cache-controller", 1}, + {"fsl,p1025-l2-cache-controller", 1}, + {"fsl,p2010-l2-cache-controller", 1}, + {"fsl,p2020-l2-cache-controller", 1}, + {"fsl,t2080-l2-cache-controller", 1}, + {"fsl,t4240-l2-cache-controller", 1}, + {0, 0} +}; + static int mpc85xx_cache_probe(device_t dev) { - if (!ofw_bus_is_compatible(dev, "cache")) + if (ofw_bus_search_compatible(dev, compats)->ocd_str == NULL) return (ENXIO); device_set_desc(dev, "MPC85xx L2 cache");
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