Date: Fri, 14 Nov 2003 11:28:19 -0800 (PST) From: Peter Wemm <peter@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 42362 for review Message-ID: <200311141928.hAEJSJVY061456@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=42362 Change 42362 by peter@peter_daintree on 2003/11/14 11:27:23 first shot at merging spurious stuff from jhb_acpipci Affected files ... .. //depot/projects/hammer/sys/amd64/amd64/apic_vector.S#6 edit .. //depot/projects/hammer/sys/amd64/amd64/local_apic.c#20 edit .. //depot/projects/hammer/sys/amd64/include/apicvar.h#12 edit .. //depot/projects/hammer/sys/amd64/include/intr_machdep.h#7 edit .. //depot/projects/hammer/sys/amd64/isa/atpic.c#21 edit .. //depot/projects/hammer/sys/amd64/isa/icu.h#11 edit Differences ... ==== //depot/projects/hammer/sys/amd64/amd64/apic_vector.S#6 (text+ko) ==== @@ -139,6 +139,8 @@ ISR_VEC(3, apic_isr3) ISR_VEC(4, apic_isr4) ISR_VEC(5, apic_isr5) + ISR_VEC(6, apic_isr6) + ISR_VEC(7, apic_isr7) MCOUNT_LABEL(eintr2) #ifdef SMP ==== //depot/projects/hammer/sys/amd64/amd64/local_apic.c#20 (text+ko) ==== @@ -60,6 +60,10 @@ */ #define MAX_APICID 16 +/* Sanity checks on IDT vectors. */ +CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS <= APIC_LOCAL_INTS); +CTASSERT(IPI_STOP < APIC_SPURIOUS_INT); + /* * Support for local APICs. Local APICs manage interrupts on each * individual processor as opposed to I/O APICs which receive interrupts @@ -105,8 +109,8 @@ IDTVEC(apic_isr3), /* 96 - 127 */ IDTVEC(apic_isr4), /* 128 - 159 */ IDTVEC(apic_isr5), /* 160 - 191 */ - NULL, /* 192 - 223 */ - NULL /* 224 - 255 */ + IDTVEC(apic_isr6), /* 192 - 223 */ + IDTVEC(apic_isr7) /* 224 - 255 */ }; volatile lapic_t *lapic; @@ -491,7 +495,7 @@ u_int vector; KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq)); - vector = irq + IDT_IO_INTS; + vector = irq + APIC_IO_INTS; if (vector >= IDT_SYSCALL) vector++; return (vector); @@ -501,12 +505,12 @@ apic_idt_to_irq(u_int vector) { - KASSERT(vector >= IDT_IO_INTS && vector != IDT_SYSCALL && - vector <= IDT_IO_INTS + NUM_IO_INTS, + KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL && + vector <= APIC_IO_INTS + NUM_IO_INTS, ("Vector %u does not map to an IRQ line", vector)); if (vector > IDT_SYSCALL) vector--; - return (vector - IDT_IO_INTS); + return (vector - APIC_IO_INTS); } /* ==== //depot/projects/hammer/sys/amd64/include/apicvar.h#12 (text+ko) ==== @@ -42,13 +42,13 @@ * Layout of local APIC interrupt vectors: * * 0xff (255) +-------------+ - * | | 15 (Spurious Vector) + * | | 15 (Spurious / IPIs / Local Interrupts) * 0xf0 (240) +-------------+ - * | | 14 (Interprocessor Interrupts) + * | | 14 (I/O Interrupts) * 0xe0 (224) +-------------+ - * | | 13 (Local Interrupt (LINT[01])) + * | | 13 (I/O Interrupts) * 0xd0 (208) +-------------+ - * | | 12 (Local Timer and Error Interrupts) + * | | 12 (I/O Interrupts) * 0xc0 (192) +-------------+ * | | 11 (I/O Interrupts) * 0xb0 (176) +-------------+ @@ -68,7 +68,7 @@ * 0x40 (64) +-------------+ * | | 3 (I/O Interrupts) * 0x30 (48) +-------------+ - * | | 2 (I/O Interrupts) + * | | 2 (ATPIC Interrupts) * 0x20 (32) +-------------+ * | | 1 (Exceptions, traps, faults, etc.) * 0x10 (16) +-------------+ @@ -80,23 +80,24 @@ */ #define APIC_ID_ALL 0xff -#define APIC_NUM_IOINTS 160 +#define APIC_NUM_IOINTS (IDT_IO_INTS + 16) +#define APIC_NUM_IOINTS 192 -#define APIC_LOCAL_INTS (IDT_IO_INTS + APIC_NUM_IOINTS) +#define APIC_LOCAL_INTS 240 #define APIC_TIMER_INT APIC_LOCAL_INTS #define APIC_ERROR_INT (APIC_LOCAL_INTS + 1) #define APIC_THERMAL_INT (APIC_LOCAL_INTS + 2) -#define APIC_IPI_INTS (APIC_LOCAL_INTS + 32) +#define APIC_IPI_INTS (APIC_LOCAL_INTS + 3) #define IPI_AST APIC_IPI_INTS /* Generate software trap. */ #define IPI_INVLTLB (APIC_IPI_INTS + 1) /* TLB Shootdown IPIs */ #define IPI_INVLPG (APIC_IPI_INTS + 2) #define IPI_INVLRNG (APIC_IPI_INTS + 3) +#define IPI_LAZYPMAP (APIC_IPI_INTS + 4) /* Lazy pmap release. */ +#define IPI_STOP (APIC_IPI_INTS + 5) /* Stop CPU until restarted. */ #define IPI_HARDCLOCK (APIC_IPI_INTS + 8) /* Inter-CPU clock handling. */ #define IPI_STATCLOCK (APIC_IPI_INTS + 9) #define IPI_RENDEZVOUS (APIC_IPI_INTS + 10) /* Inter-CPU rendezvous. */ -#define IPI_LAZYPMAP (APIC_IPI_INTS + 11) /* Lazy pmap release. */ -#define IPI_STOP (APIC_IPI_INTS + 12) /* Stop CPU until restarted. */ #define APIC_SPURIOUS_INT 255 @@ -129,7 +130,8 @@ inthand_t IDTVEC(apic_isr1), IDTVEC(apic_isr2), IDTVEC(apic_isr3), - IDTVEC(apic_isr4), IDTVEC(apic_isr5), IDTVEC(spuriousint); + IDTVEC(apic_isr4), IDTVEC(apic_isr5), IDTVEC(apic_isr6), + IDTVEC(apic_isr7), IDTVEC(spuriousint); u_int apic_irq_to_idt(u_int irq); u_int apic_idt_to_irq(u_int vector); ==== //depot/projects/hammer/sys/amd64/include/intr_machdep.h#7 (text+ko) ==== @@ -31,8 +31,8 @@ #ifdef _KERNEL -/* With I/O APIC's we can have up to 159 interrupts. */ -#define NUM_IO_INTS 159 +/* With I/O APIC's we can have up to 191 interrupts. */ +#define NUM_IO_INTS 191 #define INTRCNT_COUNT (1 + NUM_IO_INTS * 2) #ifndef LOCORE ==== //depot/projects/hammer/sys/amd64/isa/atpic.c#21 (text+ko) ==== @@ -188,15 +188,6 @@ static void atpic_enable_intr(struct intsrc *isrc) { - struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc; - struct atpic *ap = (struct atpic *)isrc->is_pic; - register_t rflags; - - mtx_lock_spin(&icu_lock); - rflags = intr_disable(); - setidt(ap->at_intbase + ai->at_irq, ai->at_intr, SDT_SYSIGT, SEL_KPL, 0); - intr_restore(rflags); - mtx_unlock_spin(&icu_lock); } static int @@ -291,6 +282,8 @@ if (i == ICU_SLAVEID) continue; ai = &atintrs[i]; + setidt(((struct atpic *)ai->at_intsrc.is_pic)->at_intbase + + ai->at_irq, ai->at_intr, SDT_SYSIGT, SEL_KPL, 0); intr_register_source(&ai->at_intsrc); } } ==== //depot/projects/hammer/sys/amd64/isa/icu.h#11 (text+ko) ==== @@ -125,7 +125,6 @@ #define ICU_SLAVEID 2 #define ICU_EOI (OCW2_EOI) /* non-specific EOI */ #define ICU_SETPRI (OCW2_R | OCW2_SL) /* set rotation priority */ -#define HWI_MASK 0xffff /* bits for h/w interrupts */ #ifndef LOCORE void atpic_handle_intr(void *cookie, struct intrframe iframe);
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