From owner-p4-projects@FreeBSD.ORG Fri Feb 22 17:44:34 2008 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id 1709E16A408; Fri, 22 Feb 2008 17:44:34 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id C72A916A406 for ; Fri, 22 Feb 2008 17:44:33 +0000 (UTC) (envelope-from rrs@cisco.com) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id C079313C442 for ; Fri, 22 Feb 2008 17:44:33 +0000 (UTC) (envelope-from rrs@cisco.com) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.1/8.14.1) with ESMTP id m1MHiXfR034348 for ; Fri, 22 Feb 2008 17:44:33 GMT (envelope-from rrs@cisco.com) Received: (from perforce@localhost) by repoman.freebsd.org (8.14.1/8.14.1/Submit) id m1MHiXhb034345 for perforce@freebsd.org; Fri, 22 Feb 2008 17:44:33 GMT (envelope-from rrs@cisco.com) Date: Fri, 22 Feb 2008 17:44:33 GMT Message-Id: <200802221744.m1MHiXhb034345@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to rrs@cisco.com using -f From: "Randall R. Stewart" To: Perforce Change Reviews Cc: Subject: PERFORCE change 135977 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 22 Feb 2008 17:44:34 -0000 http://perforce.freebsd.org/chv.cgi?CH=135977 Change 135977 by rrs@rrs-mips2-jnpr on 2008/02/22 17:44:23 tweaks to make the wheel run correctly and move things to uint64_t that should be. Affected files ... .. //depot/projects/mips2-jnpr/src/sys/mips/mips/tick.c#8 edit Differences ... ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/tick.c#8 (text+ko) ==== @@ -51,9 +51,9 @@ uint64_t counter_freq; uint64_t cycles_per_tick; -uint32_t cycles_per_usec; -uint32_t cycles_per_sec; -uint32_t cycles_per_hz; +uint64_t cycles_per_usec; +uint64_t cycles_per_sec; +uint64_t cycles_per_hz; u_int32_t counter_upper = 0; u_int32_t counter_lower_last = 0; @@ -143,7 +143,8 @@ cycles_per_tick *= 2; cycles_per_hz = counter_freq / hz; cycles_per_usec = counter_freq / (1 * 1000 * 1000); - cycles_per_sec = counter_freq / (1 * 1000); + cycles_per_sec = counter_freq ; + counter_timecounter.tc_frequency = counter_freq; /* * XXX: Some MIPS32 cores update the Count register only every two @@ -156,7 +157,7 @@ cycles_per_usec /= 2; cycles_per_sec /= 2; } - printf("hz=%d counts_per_hz:%jd counts_per_usec:%d freq:%jd cycles_per_hz:%d cycles_per_sec:%d\n", + printf("hz=%d cyl_per_hz:%jd cyl_per_usec:%jd freq:%jd cyl_per_hz:%jd cyl_per_sec:%jd\n", hz, cycles_per_tick, cycles_per_usec, @@ -249,7 +250,7 @@ } #ifdef TARGET_OCTEON -int wheel_run = 0; +int64_t wheel_run = 0; void octeon_led_run_wheel(void); @@ -268,7 +269,7 @@ * Set next clock edge. */ ltick = mips_rd_count(); - mips_wr_compare(ltick + counter_freq / hz); + mips_wr_compare(ltick + cycles_per_tick); cpu_ticks = &pcpu_ticks[PCPU_GET(cpuid)]; critical_enter(); if (ltick < counter_lower_last) {