From owner-freebsd-bugs Mon Jul 14 20:40:04 1997 Return-Path: Received: (from root@localhost) by hub.freebsd.org (8.8.5/8.8.5) id UAA02119 for bugs-outgoing; Mon, 14 Jul 1997 20:40:04 -0700 (PDT) Received: (from gnats@localhost) by hub.freebsd.org (8.8.5/8.8.5) id UAA02106; Mon, 14 Jul 1997 20:40:02 -0700 (PDT) Resent-Date: Mon, 14 Jul 1997 20:40:02 -0700 (PDT) Resent-Message-Id: <199707150340.UAA02106@hub.freebsd.org> Resent-From: gnats (GNATS Management) Resent-To: freebsd-bugs Resent-Reply-To: FreeBSD-gnats@FreeBSD.ORG, sbauer@rock.sdsmt.edu Received: from krypton.hpc.sdsmt.edu (uurock@krypton.hpc.sdsmt.edu [151.159.81.5]) by hub.freebsd.org (8.8.5/8.8.5) with ESMTP id UAA01927 for ; Mon, 14 Jul 1997 20:32:55 -0700 (PDT) Received: (from uurock@localhost) by krypton.hpc.sdsmt.edu (8.8.6/8.8.6) id VAA16560 for FreeBSD-gnats-submit@freebsd.org; Mon, 14 Jul 1997 21:32:49 -0600 Received: (from sbauer@localhost) by rock.sdsmt.edu (8.8.5/8.8.5) id VAA00374; Mon, 14 Jul 1997 21:31:58 -0600 (MDT) Message-Id: <199707150331.VAA00374@rock.sdsmt.edu> Date: Mon, 14 Jul 1997 21:31:58 -0600 (MDT) From: sbauer@rock.sdsmt.edu Reply-To: sbauer@rock.sdsmt.edu To: FreeBSD-gnats-submit@FreeBSD.ORG X-Send-Pr-Version: 3.2 Subject: i386/4092: 82371SB Chipset being configured incorrectly. Sender: owner-bugs@FreeBSD.ORG X-Loop: FreeBSD.org Precedence: bulk >Number: 4092 >Category: i386 >Synopsis: 82371SB Chipset being configured incorrectly. >Confidential: no >Severity: serious >Priority: medium >Responsible: freebsd-bugs >State: open >Class: sw-bug >Submitter-Id: current-users >Arrival-Date: Mon Jul 14 20:40:00 PDT 1997 >Last-Modified: >Originator: Steve Bauer >Organization: South Dakota School of Mines and Technology >Release: FreeBSD 2.2-STABLE i386 >Environment: FreeBSD 2.2-Stable with ctm of 345 applied. >Description: The 82371SB Chipest seems to be configured incorrectly in the file pcisupport.c The reason for this conclusion is the fact that the 82371FB (Triton I) is compatible with the 82371SB (Triton II) chipset. Yet in pcisupport.c when the 82371FB (Function 0) (0x12308086) is configured the same information is sent to the 82371SB (Function 1) (0x70108086) which is the ide controller. I do not believe this is correct since the chipsets are basically register compatible. The changes that I have made are the following: Change line 722 from 0x70108086 to 0x70008086 -- This way it will be configurting Function 0 of the 82371SB chipset. Also, I added case 70108086: at line 726 so that the function 1 (IDE interface) would be configured the same way as it is in the 82371FB chipset. >How-To-Repeat: I am not sure if this really caused much of a problem or not. It appears to have fixed some random lockups that I have been having with my machine. >Fix: Below is a patch that implements that fixes that I described above. *** pcisupport.c.orig Sun Jul 13 00:18:32 1997 --- pcisupport.c Sun Jul 13 00:19:04 1997 *************** *** 719,728 **** case 0x70308086: writeconfig (config_id, conf82437vx); break; ! case 0x70108086: case 0x122e8086: writeconfig (config_id, conf82371fb); break; case 0x12308086: writeconfig (config_id, conf82371fb2); break; --- 719,729 ---- case 0x70308086: writeconfig (config_id, conf82437vx); break; ! case 0x70008086: case 0x122e8086: writeconfig (config_id, conf82371fb); break; + case 0x70108086: case 0x12308086: writeconfig (config_id, conf82371fb2); break; >Audit-Trail: >Unformatted: