Date: Tue, 1 Sep 2020 21:41:07 +0000 (UTC) From: Mateusz Guzik <mjg@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r365116 - in head/sys/dev/ath: . ath_dfs/null ath_hal ath_hal/ah_regdomain ath_hal/ar5210 ath_hal/ar5211 ath_hal/ar5212 ath_hal/ar5312 ath_hal/ar5416 ath_hal/ar9001 ath_hal/ar9002 ath_r... Message-ID: <202009012141.081Lf7n3035488@repo.freebsd.org>
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Author: mjg Date: Tue Sep 1 21:41:07 2020 New Revision: 365116 URL: https://svnweb.freebsd.org/changeset/base/365116 Log: ath: clean up empty lines in .c and .h files Modified: head/sys/dev/ath/ah_osdep.c head/sys/dev/ath/ah_osdep_ar5210.c head/sys/dev/ath/ah_osdep_ar5211.c head/sys/dev/ath/ah_osdep_ar5212.c head/sys/dev/ath/ah_osdep_ar5416.c head/sys/dev/ath/ah_osdep_ar9300.c head/sys/dev/ath/ath_dfs/null/dfs_null.c head/sys/dev/ath/ath_hal/ah.c head/sys/dev/ath/ath_hal/ah.h head/sys/dev/ath/ath_hal/ah_eeprom_9287.c head/sys/dev/ath/ath_hal/ah_eeprom_9287.h head/sys/dev/ath/ath_hal/ah_eeprom_v14.c head/sys/dev/ath/ath_hal/ah_eeprom_v3.c head/sys/dev/ath/ath_hal/ah_eeprom_v3.h head/sys/dev/ath/ath_hal/ah_eeprom_v4k.c head/sys/dev/ath/ath_hal/ah_internal.h head/sys/dev/ath/ath_hal/ah_regdomain.c head/sys/dev/ath/ath_hal/ah_regdomain/ah_rd_domains.h head/sys/dev/ath/ath_hal/ah_regdomain/ah_rd_freqbands.h head/sys/dev/ath/ath_hal/ah_soc.h head/sys/dev/ath/ath_hal/ar5210/ar5210_recv.c head/sys/dev/ath/ath_hal/ar5210/ar5210_reset.c head/sys/dev/ath/ath_hal/ar5211/ar5211_keycache.c head/sys/dev/ath/ath_hal/ar5211/ar5211_misc.c head/sys/dev/ath/ath_hal/ar5211/ar5211_phy.c head/sys/dev/ath/ath_hal/ar5211/ar5211_recv.c head/sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c head/sys/dev/ath/ath_hal/ar5211/ar5211phy.h head/sys/dev/ath/ath_hal/ar5211/ar5211reg.h head/sys/dev/ath/ath_hal/ar5212/ar2316.c head/sys/dev/ath/ath_hal/ar5212/ar2317.c head/sys/dev/ath/ath_hal/ar5212/ar2413.c head/sys/dev/ath/ath_hal/ar5212/ar2425.c head/sys/dev/ath/ath_hal/ar5212/ar5111.c head/sys/dev/ath/ath_hal/ar5212/ar5112.c head/sys/dev/ath/ath_hal/ar5212/ar5212_ani.c head/sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c head/sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c head/sys/dev/ath/ath_hal/ar5212/ar5212_misc.c head/sys/dev/ath/ath_hal/ar5212/ar5212_phy.c head/sys/dev/ath/ath_hal/ar5212/ar5212_reset.c head/sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c head/sys/dev/ath/ath_hal/ar5212/ar5212phy.h head/sys/dev/ath/ath_hal/ar5212/ar5413.c head/sys/dev/ath/ath_hal/ar5312/ar5312_eeprom.c head/sys/dev/ath/ath_hal/ar5312/ar5312_gpio.c head/sys/dev/ath/ath_hal/ar5312/ar5312_interrupts.c head/sys/dev/ath/ath_hal/ar5312/ar5312_reset.c head/sys/dev/ath/ath_hal/ar5312/ar5312reg.h head/sys/dev/ath/ath_hal/ar5312/ar5315_gpio.c head/sys/dev/ath/ath_hal/ar5416/ar2133.c head/sys/dev/ath/ath_hal/ar5416/ar5416_ani.c head/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c head/sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c head/sys/dev/ath/ath_hal/ar5416/ar5416_cal.c head/sys/dev/ath/ath_hal/ar5416/ar5416_cal.h head/sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c head/sys/dev/ath/ath_hal/ar5416/ar5416_power.c head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c head/sys/dev/ath/ath_hal/ar5416/ar5416_spectral.c head/sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c head/sys/dev/ath/ath_hal/ar5416/ar5416desc.h head/sys/dev/ath/ath_hal/ar5416/ar5416reg.h head/sys/dev/ath/ath_hal/ar9001/ar9130_attach.c head/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c head/sys/dev/ath/ath_hal/ar9002/ar9280_olc.c head/sys/dev/ath/ath_hal/ar9002/ar9285.c head/sys/dev/ath/ath_hal/ar9002/ar9285_attach.c head/sys/dev/ath/ath_hal/ar9002/ar9285_btcoex.c head/sys/dev/ath/ath_hal/ar9002/ar9285_diversity.c head/sys/dev/ath/ath_hal/ar9002/ar9285_reset.c head/sys/dev/ath/ath_hal/ar9002/ar9287_attach.c head/sys/dev/ath/ath_hal/ar9002/ar9287_cal.c head/sys/dev/ath/ath_hal/ar9002/ar9287_reset.c head/sys/dev/ath/ath_rate/amrr/amrr.c head/sys/dev/ath/ath_rate/onoe/onoe.c head/sys/dev/ath/ath_rate/sample/sample.c head/sys/dev/ath/ath_rate/sample/sample.h head/sys/dev/ath/if_ath.c head/sys/dev/ath/if_ath_ahb.c head/sys/dev/ath/if_ath_beacon.c head/sys/dev/ath/if_ath_beacon.h head/sys/dev/ath/if_ath_btcoex.c head/sys/dev/ath/if_ath_dfs.c head/sys/dev/ath/if_ath_drv.c head/sys/dev/ath/if_ath_ioctl.c head/sys/dev/ath/if_ath_led.c head/sys/dev/ath/if_ath_lna_div.c head/sys/dev/ath/if_ath_pci.c head/sys/dev/ath/if_ath_pci_devlist.h head/sys/dev/ath/if_ath_rate.c head/sys/dev/ath/if_ath_spectral.c head/sys/dev/ath/if_ath_sysctl.c head/sys/dev/ath/if_ath_tx.c head/sys/dev/ath/if_ath_tx.h head/sys/dev/ath/if_ath_tx_edma.c head/sys/dev/ath/if_ath_tx_ht.c head/sys/dev/ath/if_athioctl.h head/sys/dev/ath/if_athvar.h Modified: head/sys/dev/ath/ah_osdep.c ============================================================================== --- head/sys/dev/ath/ah_osdep.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ah_osdep.c Tue Sep 1 21:41:07 2020 (r365116) @@ -447,7 +447,6 @@ ath_hal_modevent(module_t mod __unused, int type, void default: error = EOPNOTSUPP; break; - } return (error); } Modified: head/sys/dev/ath/ah_osdep_ar5210.c ============================================================================== --- head/sys/dev/ath/ah_osdep_ar5210.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ah_osdep_ar5210.c Tue Sep 1 21:41:07 2020 (r365116) @@ -64,7 +64,6 @@ ath_hal_ar5210_modevent(module_t mod __unused, int typ default: error = EOPNOTSUPP; break; - } return (error); } Modified: head/sys/dev/ath/ah_osdep_ar5211.c ============================================================================== --- head/sys/dev/ath/ah_osdep_ar5211.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ah_osdep_ar5211.c Tue Sep 1 21:41:07 2020 (r365116) @@ -64,7 +64,6 @@ ath_hal_ar5211_modevent(module_t mod __unused, int typ default: error = EOPNOTSUPP; break; - } return (error); } Modified: head/sys/dev/ath/ah_osdep_ar5212.c ============================================================================== --- head/sys/dev/ath/ah_osdep_ar5212.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ah_osdep_ar5212.c Tue Sep 1 21:41:07 2020 (r365116) @@ -85,7 +85,6 @@ ath_hal_ar5212_modevent(module_t mod __unused, int typ default: error = EOPNOTSUPP; break; - } return (error); } Modified: head/sys/dev/ath/ah_osdep_ar5416.c ============================================================================== --- head/sys/dev/ath/ah_osdep_ar5416.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ah_osdep_ar5416.c Tue Sep 1 21:41:07 2020 (r365116) @@ -92,7 +92,6 @@ ath_hal_ar5416_modevent(module_t mod __unused, int typ default: error = EOPNOTSUPP; break; - } return (error); } Modified: head/sys/dev/ath/ah_osdep_ar9300.c ============================================================================== --- head/sys/dev/ath/ah_osdep_ar9300.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ah_osdep_ar9300.c Tue Sep 1 21:41:07 2020 (r365116) @@ -64,7 +64,6 @@ ath_hal_ar9300_modevent(module_t mod __unused, int typ default: error = EOPNOTSUPP; break; - } return (error); } Modified: head/sys/dev/ath/ath_dfs/null/dfs_null.c ============================================================================== --- head/sys/dev/ath/ath_dfs/null/dfs_null.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_dfs/null/dfs_null.c Tue Sep 1 21:41:07 2020 (r365116) @@ -54,7 +54,7 @@ __FBSDID("$FreeBSD$"); #include <sys/bus.h> #include <sys/socket.h> - + #include <net/if.h> #include <net/if_var.h> #include <net/if_media.h> Modified: head/sys/dev/ath/ath_hal/ah.c ============================================================================== --- head/sys/dev/ath/ath_hal/ah.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ah.c Tue Sep 1 21:41:07 2020 (r365116) @@ -556,7 +556,6 @@ ath_hal_get_curmode(struct ath_hal *ah, const struct i return HAL_MODE_11NG_HT20; } - typedef enum { WIRELESS_MODE_11a = 0, WIRELESS_MODE_TURBO = 1, @@ -971,7 +970,7 @@ ath_hal_getregdump(struct ath_hal *ah, const HAL_REGRA } return (char *) dp - (char *) dstbuf; } - + static void ath_hal_setregs(struct ath_hal *ah, const HAL_REGWRITE *regs, int space) { Modified: head/sys/dev/ath/ath_hal/ah.h ============================================================================== --- head/sys/dev/ath/ath_hal/ah.h Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ah.h Tue Sep 1 21:41:07 2020 (r365116) @@ -739,7 +739,6 @@ typedef enum { HAL_HT_EXTPROTSPACING_25 = 1, /* 25 MHz spacing */ } HAL_HT_EXTPROTSPACING; - typedef enum { HAL_RX_CLEAR_CTL_LOW = 0x1, /* force control channel to appear busy */ HAL_RX_CLEAR_EXT_LOW = 0x2, /* force extension channel to appear busy */ @@ -1052,7 +1051,6 @@ typedef enum { HAL_DFS_ETSI_DOMAIN = 2, /* ETSI dfs domain */ HAL_DFS_MKK4_DOMAIN = 3, /* Japan dfs domain */ } HAL_DFS_DOMAIN; - /* * MFP decryption options for initializing the MAC. Modified: head/sys/dev/ath/ath_hal/ah_eeprom_9287.c ============================================================================== --- head/sys/dev/ath/ath_hal/ah_eeprom_9287.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ah_eeprom_9287.c Tue Sep 1 21:41:07 2020 (r365116) @@ -207,11 +207,11 @@ static uint16_t v9287EepromGetSpurChan(struct ath_hal *ah, int ix, HAL_BOOL is2GHz) { HAL_EEPROM_9287 *ee = AH_PRIVATE(ah)->ah_eeprom; - + HALASSERT(is2GHz == AH_TRUE); if (is2GHz != AH_TRUE) return 0; /* XXX ? */ - + HALASSERT(0 <= ix && ix < AR5416_EEPROM_MODAL_SPURS); return ee->ee_base.modalHeader.spurChans[ix].spurChan; } @@ -234,7 +234,6 @@ fbin2freq(uint8_t fbin, HAL_BOOL is2GHz) return (uint16_t)((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin)); } - /* * Copy EEPROM Conformance Testing Limits contents * into the allocated space @@ -247,7 +246,7 @@ v9287EepromReadCTLInfo(struct ath_hal *ah, HAL_EEPROM_ { RD_EDGES_POWER *rep = ee->ee_rdEdgesPower; int i, j; - + HALASSERT(AR9287_NUM_CTLS <= sizeof(ee->ee_rdEdgesPower)/NUM_EDGES); for (i = 0; ee->ee_base.ctlIndex[i] != 0 && i < AR9287_NUM_CTLS; i++) { @@ -359,7 +358,7 @@ ath_hal_9287EepromAttach(struct ath_hal *ah) len = ee->ee_base.baseEepHeader.length; } len = AH_MIN(len, sizeof(HAL_EEPROM_9287)) / sizeof(uint16_t); - + /* Apply the checksum, done in native eeprom format */ /* XXX - Need to check to make sure checksum calculation is done * in the correct endian format. Right now, it seems it would Modified: head/sys/dev/ath/ath_hal/ah_eeprom_9287.h ============================================================================== --- head/sys/dev/ath/ath_hal/ah_eeprom_9287.h Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ah_eeprom_9287.h Tue Sep 1 21:41:07 2020 (r365116) @@ -166,5 +166,4 @@ typedef struct { typedef struct modal_eep_ar9287_header MODAL_EEP_9287_HEADER; typedef struct base_eep_ar9287_header BASE_EEP_9287_HEADER; - #endif /* __AH_EEPROM_9287_H__ */ Modified: head/sys/dev/ath/ath_hal/ah_eeprom_v14.c ============================================================================== --- head/sys/dev/ath/ath_hal/ah_eeprom_v14.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ah_eeprom_v14.c Tue Sep 1 21:41:07 2020 (r365116) @@ -249,7 +249,7 @@ static uint16_t v14EepromGetSpurChan(struct ath_hal *ah, int ix, HAL_BOOL is2GHz) { HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom; - + HALASSERT(0 <= ix && ix < AR5416_EEPROM_MODAL_SPURS); return ee->ee_base.modalHeader[is2GHz].spurChans[ix].spurChan; } @@ -284,7 +284,7 @@ v14EepromReadCTLInfo(struct ath_hal *ah, HAL_EEPROM_v1 { RD_EDGES_POWER *rep = ee->ee_rdEdgesPower; int i, j; - + HALASSERT(AR5416_NUM_CTLS <= sizeof(ee->ee_rdEdgesPower)/NUM_EDGES); for (i = 0; ee->ee_base.ctlIndex[i] != 0 && i < AR5416_NUM_CTLS; i++) { @@ -342,7 +342,7 @@ ath_hal_v14EepromAttach(struct ath_hal *ah) uint32_t sum; HALASSERT(ee == AH_NULL); - + /* * Don't check magic if we're supplied with an EEPROM block, * typically this is from Howl but it may also be from later @@ -398,7 +398,7 @@ ath_hal_v14EepromAttach(struct ath_hal *ah) len = ee->ee_base.baseEepHeader.length; } len = AH_MIN(len, sizeof(struct ar5416eeprom)) / sizeof(uint16_t); - + /* Apply the checksum, done in native eeprom format */ /* XXX - Need to check to make sure checksum calculation is done * in the correct endian format. Right now, it seems it would Modified: head/sys/dev/ath/ath_hal/ah_eeprom_v3.c ============================================================================== --- head/sys/dev/ath/ath_hal/ah_eeprom_v3.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ah_eeprom_v3.c Tue Sep 1 21:41:07 2020 (r365116) @@ -739,14 +739,14 @@ readEepromRawPowerCalInfo2413(struct ath_hal *ah, HAL_ int numEEPROMWordsPerChannel; uint32_t off; HAL_BOOL ret = AH_FALSE; - + HALASSERT(ee->ee_version >= AR_EEPROM_VER5_0); HALASSERT(ee->ee_eepMap == 2); - + pCal = ath_hal_malloc(sizeof(EEPROM_DATA_STRUCT_2413)); if (pCal == AH_NULL) goto exit; - + off = ee->ee_eepMap2PowerCalStart; if (ee->ee_Amode) { OS_MEMZERO(pCal, sizeof(EEPROM_DATA_STRUCT_2413)); Modified: head/sys/dev/ath/ath_hal/ah_eeprom_v3.h ============================================================================== --- head/sys/dev/ath/ath_hal/ah_eeprom_v3.h Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ah_eeprom_v3.h Tue Sep 1 21:41:07 2020 (r365116) @@ -231,7 +231,6 @@ typedef struct cornerCalInfo { #define NUM_TARGET_POWER_LOCATIONS_11B 4 #define NUM_TARGET_POWER_LOCATIONS_11G 6 - typedef struct { uint16_t xpd_gain; uint16_t numPcdacs; Modified: head/sys/dev/ath/ath_hal/ah_eeprom_v4k.c ============================================================================== --- head/sys/dev/ath/ath_hal/ah_eeprom_v4k.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ah_eeprom_v4k.c Tue Sep 1 21:41:07 2020 (r365116) @@ -200,7 +200,7 @@ static uint16_t v4kEepromGetSpurChan(struct ath_hal *ah, int ix, HAL_BOOL is2GHz) { HAL_EEPROM_v4k *ee = AH_PRIVATE(ah)->ah_eeprom; - + HALASSERT(0 <= ix && ix < AR5416_EEPROM_MODAL_SPURS); HALASSERT(is2GHz); return ee->ee_base.modalHeader.spurChans[ix].spurChan; @@ -236,7 +236,7 @@ v4kEepromReadCTLInfo(struct ath_hal *ah, HAL_EEPROM_v4 { RD_EDGES_POWER *rep = ee->ee_rdEdgesPower; int i, j; - + HALASSERT(AR5416_4K_NUM_CTLS <= sizeof(ee->ee_rdEdgesPower)/NUM_EDGES); for (i = 0; ee->ee_base.ctlIndex[i] != 0 && i < AR5416_4K_NUM_CTLS; i++) { @@ -347,7 +347,7 @@ ath_hal_v4kEepromAttach(struct ath_hal *ah) len = ee->ee_base.baseEepHeader.length; } len = AH_MIN(len, sizeof(struct ar5416eeprom_4k)) / sizeof(uint16_t); - + /* Apply the checksum, done in native eeprom format */ /* XXX - Need to check to make sure checksum calculation is done * in the correct endian format. Right now, it seems it would Modified: head/sys/dev/ath/ath_hal/ah_internal.h ============================================================================== --- head/sys/dev/ath/ath_hal/ah_internal.h Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ah_internal.h Tue Sep 1 21:41:07 2020 (r365116) @@ -849,7 +849,6 @@ typedef struct { uint16_t ee_data; /* write data */ } HAL_DIAG_EEVAL; - typedef struct { u_int offset; /* reg offset */ uint32_t val; /* reg value */ Modified: head/sys/dev/ath/ath_hal/ah_regdomain.c ============================================================================== --- head/sys/dev/ath/ath_hal/ah_regdomain.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ah_regdomain.c Tue Sep 1 21:41:07 2020 (r365116) @@ -953,7 +953,6 @@ ath_hal_getctl(struct ath_hal *ah, const struct ieee80 return ctl; } - /* * Update the current dfsDomain setting based on the given * country code. @@ -978,7 +977,6 @@ ath_hal_update_dfsdomain(struct ath_hal *ah) HALDEBUG(ah, HAL_DEBUG_REGDOMAIN, "%s ah_dfsDomain: %d\n", __func__, AH_PRIVATE(ah)->ah_dfsDomain); } - /* * Return the max allowed antenna gain and apply any regulatory Modified: head/sys/dev/ath/ath_hal/ah_regdomain/ah_rd_domains.h ============================================================================== --- head/sys/dev/ath/ath_hal/ah_regdomain/ah_rd_domains.h Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ah_regdomain/ah_rd_domains.h Tue Sep 1 21:41:07 2020 (r365116) @@ -64,7 +64,6 @@ W1(_fg) | W1(_fh) | W1(_fi) } static REG_DOMAIN regDomains[] = { - {.regDmnEnum = DEBUG_REG_DMN, .conformanceTestLimit = FCC, .dfsMask = DFS_FCC3, Modified: head/sys/dev/ath/ath_hal/ah_regdomain/ah_rd_freqbands.h ============================================================================== --- head/sys/dev/ath/ath_hal/ah_regdomain/ah_rd_freqbands.h Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ah_regdomain/ah_rd_freqbands.h Tue Sep 1 21:41:07 2020 (r365116) @@ -198,7 +198,6 @@ static REG_DMN_FREQ_BAND regDmn5GhzFreq[] = { #define W2_5825_5825 AFTER(W2_5180_5240) }; - /* * 5GHz Turbo (dynamic & static) tags */ @@ -373,7 +372,7 @@ static REG_DMN_FREQ_BAND regDmn2Ghz11gFreq[] = { #define G3_2412_2462 AFTER(G2_2412_2462) { 2412, 2462, 27, 6, 5, 5, NO_DFS, NO_PSCAN }, #define G4_2412_2462 AFTER(G3_2412_2462) - + { 2432, 2442, 20, 0, 20, 5, NO_DFS, NO_PSCAN }, #define G1_2432_2442 AFTER(G4_2412_2462) Modified: head/sys/dev/ath/ath_hal/ah_soc.h ============================================================================== --- head/sys/dev/ath/ath_hal/ah_soc.h Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ah_soc.h Tue Sep 1 21:41:07 2020 (r365116) @@ -62,18 +62,18 @@ struct ar531x_boarddata { #define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */ uint16_t resetConfigGpio; /* Reset factory GPIO pin */ uint16_t sysLedGpio; /* System LED GPIO pin */ - + uint32_t cpuFreq; /* CPU core frequency in Hz */ uint32_t sysFreq; /* System frequency in Hz */ uint32_t cntFreq; /* Calculated C0_COUNT frequency */ - + uint8_t wlan0Mac[6]; uint8_t enet0Mac[6]; uint8_t enet1Mac[6]; - + uint16_t pciId; /* Pseudo PCIID for common code */ uint16_t memCap; /* cap bank1 in MB */ - + /* version 3 */ uint8_t wlan1Mac[6]; /* (ar5212) */ }; Modified: head/sys/dev/ath/ath_hal/ar5210/ar5210_recv.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5210/ar5210_recv.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5210/ar5210_recv.c Tue Sep 1 21:41:07 2020 (r365116) @@ -50,7 +50,6 @@ ar5210SetRxDP(struct ath_hal *ah, uint32_t rxdp, HAL_R OS_REG_WRITE(ah, AR_RXDP, rxdp); } - /* * Set Receive Enable bits. */ Modified: head/sys/dev/ath/ath_hal/ar5210/ar5210_reset.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5210/ar5210_reset.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5210/ar5210_reset.c Tue Sep 1 21:41:07 2020 (r365116) @@ -611,7 +611,6 @@ ar5210SetResetReg(struct ath_hal *ah, uint32_t resetMa return rt; } - /* * Returns: the pcdac value */ Modified: head/sys/dev/ath/ath_hal/ar5211/ar5211_keycache.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5211/ar5211_keycache.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5211/ar5211_keycache.c Tue Sep 1 21:41:07 2020 (r365116) @@ -163,7 +163,6 @@ ar5211SetKeyCacheEntry(struct ath_hal *ah, uint16_t en if (k->kv_len <= 104 / NBBY) key4 &= 0xff; - /* * Note: WEP key cache hardware requires that each double-word * pair be written in even/odd order (since the destination is Modified: head/sys/dev/ath/ath_hal/ar5211/ar5211_misc.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5211/ar5211_misc.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5211/ar5211_misc.c Tue Sep 1 21:41:07 2020 (r365116) @@ -708,7 +708,6 @@ ar5211Get11nExtBusy(struct ath_hal *ah) return (0); } - /* * There's no channel survey support for the AR5211. */ Modified: head/sys/dev/ath/ath_hal/ar5211/ar5211_phy.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5211/ar5211_phy.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5211/ar5211_phy.c Tue Sep 1 21:41:07 2020 (r365116) @@ -81,7 +81,6 @@ HAL_RATE_TABLE ar5211_11b_table = { #undef CCK #undef TURBO - const HAL_RATE_TABLE * ar5211GetRateTable(struct ath_hal *ah, u_int mode) { Modified: head/sys/dev/ath/ath_hal/ar5211/ar5211_recv.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5211/ar5211_recv.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5211/ar5211_recv.c Tue Sep 1 21:41:07 2020 (r365116) @@ -51,7 +51,6 @@ ar5211SetRxDP(struct ath_hal *ah, uint32_t rxdp, HAL_R HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp); } - /* * Set Receive Enable bits. */ Modified: head/sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5211/ar5211_xmit.c Tue Sep 1 21:41:07 2020 (r365116) @@ -193,7 +193,6 @@ setTxQInterrupts(struct ath_hal *ah, HAL_TX_QUEUE_INFO AR_IMR_S2_QCU_TXURN, ahp->ah_txUrnInterruptMask); } - /* * Free a tx DCU/QCU combination. */ @@ -676,7 +675,6 @@ ar5211GetTxCompletionRates(struct ath_hal *ah, const s { return AH_FALSE; } - void ar5211SetTxDescLink(struct ath_hal *ah, void *ds, uint32_t link) Modified: head/sys/dev/ath/ath_hal/ar5211/ar5211phy.h ============================================================================== --- head/sys/dev/ath/ath_hal/ar5211/ar5211phy.h Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5211/ar5211phy.h Tue Sep 1 21:41:07 2020 (r365116) @@ -48,7 +48,6 @@ #define AR_PHY_PLL_CTL_40 0x18 /* 40 MHz */ #define AR_PHY_PLL_CTL_20 0x13 /* 20 MHz half rate 11a for emulation */ - #define AR_PHY_RX_DELAY 0x9914 /* PHY analog_power_on_time, in 100ns increments */ #define AR_PHY_RX_DELAY_M 0x00003FFF /* Mask for delay from active assertion (wake up) */ /* to enable_receiver */ Modified: head/sys/dev/ath/ath_hal/ar5211/ar5211reg.h ============================================================================== --- head/sys/dev/ath/ath_hal/ar5211/ar5211reg.h Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5211/ar5211reg.h Tue Sep 1 21:41:07 2020 (r365116) @@ -808,7 +808,6 @@ #define AR5211_USEC_RX_LAT_M 0x1F800000 /* Rx latency */ #define AR5211_USEC_RX_LAT_S 23 - #define AR_BEACON_PERIOD 0x0000FFFF /* Beacon period in TU/msec */ #define AR_BEACON_PERIOD_S 0 /* Byte offset of PERIOD start*/ #define AR_BEACON_TIM 0x007F0000 /* Byte offset of TIM start */ Modified: head/sys/dev/ath/ath_hal/ar5212/ar2316.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5212/ar2316.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5212/ar2316.c Tue Sep 1 21:41:07 2020 (r365116) @@ -629,7 +629,7 @@ ar2316GetMaxPower(struct ath_hal *ah, const RAW_DATA_P { uint32_t ii; uint16_t Pmax=0,numVpd; - + for (ii=0; ii< MAX_NUM_PDGAINS_PER_CHANNEL; ii++) { /* work forwards cuase lowest pdGain for highest power */ numVpd = data->pDataPerPDGain[ii].numVpd; @@ -664,7 +664,7 @@ ar2316GetChannelMaxMinPower(struct ath_hal *ah, numChannels = pRawDataset->numChannels; data = pRawDataset->pDataPerChannel; - + /* Make sure the channel is in the range of the TP values * (freq piers) */ Modified: head/sys/dev/ath/ath_hal/ar5212/ar2317.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5212/ar2317.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5212/ar2317.c Tue Sep 1 21:41:07 2020 (r365116) @@ -608,7 +608,7 @@ ar2317GetMaxPower(struct ath_hal *ah, const RAW_DATA_P uint32_t ii; uint16_t Pmax=0,numVpd; uint16_t vpdmax; - + for (ii=0; ii< MAX_NUM_PDGAINS_PER_CHANNEL; ii++) { /* work forwards cuase lowest pdGain for highest power */ numVpd = data->pDataPerPDGain[ii].numVpd; @@ -644,7 +644,7 @@ ar2317GetChannelMaxMinPower(struct ath_hal *ah, numChannels = pRawDataset->numChannels; data = pRawDataset->pDataPerChannel; - + /* Make sure the channel is in the range of the TP values * (freq piers) */ Modified: head/sys/dev/ath/ath_hal/ar5212/ar2413.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5212/ar2413.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5212/ar2413.c Tue Sep 1 21:41:07 2020 (r365116) @@ -624,7 +624,7 @@ ar2413GetMaxPower(struct ath_hal *ah, const RAW_DATA_P { uint32_t ii; uint16_t Pmax=0,numVpd; - + for (ii=0; ii< MAX_NUM_PDGAINS_PER_CHANNEL; ii++) { /* work forwards cuase lowest pdGain for highest power */ numVpd = data->pDataPerPDGain[ii].numVpd; @@ -659,7 +659,7 @@ ar2413GetChannelMaxMinPower(struct ath_hal *ah, numChannels = pRawDataset->numChannels; data = pRawDataset->pDataPerChannel; - + /* Make sure the channel is in the range of the TP values * (freq piers) */ Modified: head/sys/dev/ath/ath_hal/ar5212/ar2425.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5212/ar2425.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5212/ar2425.c Tue Sep 1 21:41:07 2020 (r365116) @@ -492,7 +492,6 @@ ar2425getGainBoundariesAndPdadcsForPowers(struct ath_h HALDEBUG(ah, HAL_DEBUG_RFPARAM, "<==%s\n", __func__); } - /* Same as 2413 set power table */ static HAL_BOOL ar2425SetPowerTable(struct ath_hal *ah, @@ -586,7 +585,7 @@ ar2425GetMaxPower(struct ath_hal *ah, const RAW_DATA_P { uint32_t ii; uint16_t Pmax=0,numVpd; - + for (ii=0; ii< MAX_NUM_PDGAINS_PER_CHANNEL; ii++) { /* work forwards cuase lowest pdGain for highest power */ numVpd = data->pDataPerPDGain[ii].numVpd; @@ -622,7 +621,7 @@ ar2425GetChannelMaxMinPower(struct ath_hal *ah, numChannels = pRawDataset->numChannels; data = pRawDataset->pDataPerChannel; - + /* Make sure the channel is in the range of the TP values * (freq piers) */ Modified: head/sys/dev/ath/ath_hal/ar5212/ar5111.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5212/ar5111.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5212/ar5111.c Tue Sep 1 21:41:07 2020 (r365116) @@ -336,7 +336,6 @@ ar5111SetRfRegs(struct ath_hal *ah, const struct ieee8 ar5212ModifyRfBuffer(rfReg, rfWaitS, 5, 19, 0); ar5212ModifyRfBuffer(rfReg, rfWaitI, 5, 24, 0); ar5212ModifyRfBuffer(rfReg, rfMaxTime, 2, 49, 0); - } HAL_INI_WRITE_BANK(ah, ar5212Bank7_5111, rfReg, regWrites); Modified: head/sys/dev/ath/ath_hal/ar5212/ar5112.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5212/ar5112.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5212/ar5112.c Tue Sep 1 21:41:07 2020 (r365116) @@ -281,7 +281,7 @@ ar5112SetRfRegs(struct ath_hal *ah, ar5212ModifyRfBuffer(priv->Bank6Data, ob5GHz, 3, 279, 0); ar5212ModifyRfBuffer(priv->Bank6Data, db5GHz, 3, 282, 0); } - + /* Lower synth voltage for X112 Rev 2.0 only */ if (IS_RADX112_REV2(ah)) { /* Non-Reversed analyg registers - so values are pre-reversed */ @@ -763,7 +763,7 @@ ar5112GetMinPower(struct ath_hal *ah, const EXPN_DATA_ retVal = minPwr - (minPcdac*2); return(retVal); } - + static HAL_BOOL ar5112GetChannelMaxMinPower(struct ath_hal *ah, const struct ieee80211_channel *chan, Modified: head/sys/dev/ath/ath_hal/ar5212/ar5212_ani.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5212/ar5212_ani.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5212/ar5212_ani.c Tue Sep 1 21:41:07 2020 (r365116) @@ -225,7 +225,7 @@ ar5212AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, struct ath_hal_5212 *ahp = AH5212(ah); struct ar5212AniState *aniState = ahp->ah_curani; const struct ar5212AniParams *params = AH_NULL; - + /* * This function may be called before there's a current * channel (eg to disable ANI.) @@ -784,7 +784,7 @@ ar5212AniLowerImmunity(struct ath_hal *ah) struct ath_hal_5212 *ahp = AH5212(ah); struct ar5212AniState *aniState; const struct ar5212AniParams *params; - + HALASSERT(ANI_ENA(ah)); aniState = ahp->ah_curani; Modified: head/sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5212/ar5212_interrupts.c Tue Sep 1 21:41:07 2020 (r365116) @@ -27,7 +27,6 @@ #include "ar5212/ar5212reg.h" #include "ar5212/ar5212phy.h" - /* * Checks to see if an interrupt is pending on our NIC * Modified: head/sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5212/ar5212_keycache.c Tue Sep 1 21:41:07 2020 (r365116) @@ -245,7 +245,6 @@ ar5212SetKeyCacheEntry(struct ath_hal *ah, uint16_t en OS_REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); (void) ar5212SetKeyCacheEntryMac(ah, entry, mac); - /* * Write MIC entry according to new or old key layout. * The MISC_MODE register is assumed already set so Modified: head/sys/dev/ath/ath_hal/ar5212/ar5212_misc.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5212/ar5212_misc.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5212/ar5212_misc.c Tue Sep 1 21:41:07 2020 (r365116) @@ -623,7 +623,7 @@ ar5212SetCoverageClass(struct ath_hal *ah, uint8_t cov * timeouts. This value is in core clocks. */ timeout = ACK_CTS_TIMEOUT_11A + (coverageclass * 3 * clkRate); - + /* * Write the values: slot, eifs, ack/cts timeouts. */ @@ -1194,7 +1194,6 @@ ar5212EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM * val &= ~ AR_PHY_RADAR_0_ENA; if (IS_5413(ah)) { - if (pe->pe_blockradar == 1) OS_REG_SET_BIT(ah, AR_PHY_RADAR_2, AR_PHY_RADAR_2_BLOCKOFDMWEAK); Modified: head/sys/dev/ath/ath_hal/ar5212/ar5212_phy.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5212/ar5212_phy.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5212/ar5212_phy.c Tue Sep 1 21:41:07 2020 (r365116) @@ -129,7 +129,6 @@ HAL_RATE_TABLE ar5212_11b_table = { }, }; - /* Venice TODO: roundUpRate() is broken when the rate table does not represent rates * in increasing order e.g. 5.5, 11, 6, 9. * An average rate of 6 Mbps will currently map to 11 Mbps. Modified: head/sys/dev/ath/ath_hal/ar5212/ar5212_reset.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5212/ar5212_reset.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5212/ar5212_reset.c Tue Sep 1 21:41:07 2020 (r365116) @@ -692,7 +692,7 @@ done: HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__); RESTORE_CCK(ah, chan, isBmode); - + OS_MARK(ah, AH_MARK_RESET_DONE, 0); return AH_TRUE; @@ -1192,7 +1192,6 @@ ar5212MacStop(struct ath_hal *ah) return status; } - /* * Write the given reset bit mask into the reset register */ @@ -1922,7 +1921,6 @@ ar5212SetSpurMitigation(struct ath_hal *ah, } #undef CHAN_TO_SPUR } - /* * Delta slope coefficient computation. Modified: head/sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5212/ar5212_xmit.c Tue Sep 1 21:41:07 2020 (r365116) @@ -107,7 +107,6 @@ ar5212GetTxQueueProps(struct ath_hal *ah, int q, HAL_T struct ath_hal_5212 *ahp = AH5212(ah); HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; - if (q >= pCap->halTotalQueues) { HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid queue num %u\n", __func__, q); @@ -346,7 +345,7 @@ ar5212ResetTxQueue(struct ath_hal *ah, u_int q) SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_INT) | AR_Q_RDYTIMECFG_ENA); } - + OS_REG_WRITE(ah, AR_DCHNTIME(q), SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) | (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0)); @@ -473,7 +472,7 @@ ar5212ResetTxQueue(struct ath_hal *ah, u_int q) OS_REG_READ(ah, AR_Q0_MISC + 4*q) | AR_Q_MISC_QCU_COMP_EN); } - + /* * Always update the secondary interrupt mask registers - this * could be a new queue getting enabled in a running system or Modified: head/sys/dev/ath/ath_hal/ar5212/ar5212phy.h ============================================================================== --- head/sys/dev/ath/ath_hal/ar5212/ar5212phy.h Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5212/ar5212phy.h Tue Sep 1 21:41:07 2020 (r365116) @@ -78,7 +78,6 @@ #define AR_PHY_TSTDAC_CONST_Q_S 9 #define AR_PHY_TSTDAC_CONST_I 0x000001FF - #define AR_PHY_SETTLING 0x9844 #define AR_PHY_SETTLING_AGC 0x0000007F #define AR_PHY_SETTLING_AGC_S 0 Modified: head/sys/dev/ath/ath_hal/ar5212/ar5413.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5212/ar5413.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5212/ar5413.c Tue Sep 1 21:41:07 2020 (r365116) @@ -241,7 +241,6 @@ ar5413SetRfRegs(struct ath_hal *ah, } else { ar5212ModifyRfBuffer(priv->Bank6Data, ob5GHz, 3, 247, 0); ar5212ModifyRfBuffer(priv->Bank6Data, db5GHz, 3, 244, 0); - } /* Bank 7 Setup */ @@ -668,7 +667,7 @@ ar5413GetMaxPower(struct ath_hal *ah, const RAW_DATA_P { uint32_t ii; uint16_t Pmax=0,numVpd; - + for (ii=0; ii< MAX_NUM_PDGAINS_PER_CHANNEL; ii++) { /* work forwards cuase lowest pdGain for highest power */ numVpd = data->pDataPerPDGain[ii].numVpd; @@ -705,7 +704,7 @@ ar5413GetChannelMaxMinPower(struct ath_hal *ah, numChannels = pRawDataset->numChannels; data = pRawDataset->pDataPerChannel; - + /* Make sure the channel is in the range of the TP values * (freq piers) */ Modified: head/sys/dev/ath/ath_hal/ar5312/ar5312_eeprom.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5312/ar5312_eeprom.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5312/ar5312_eeprom.c Tue Sep 1 21:41:07 2020 (r365116) @@ -20,7 +20,6 @@ */ #include "opt_ah.h" - #ifdef AH_SUPPORT_AR5312 #include "ah.h" @@ -39,7 +38,7 @@ ar5312EepromRead(struct ath_hal *ah, u_int off, uint16 int i,offset; const char *eepromAddr = AR5312_RADIOCONFIG(ah); uint8_t *data; - + data = (uint8_t *) dataIn; for (i=0,offset=2*off; i<2; i++,offset++) { data[i] = eepromAddr[offset]; Modified: head/sys/dev/ath/ath_hal/ar5312/ar5312_gpio.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5312/ar5312_gpio.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5312/ar5312_gpio.c Tue Sep 1 21:41:07 2020 (r365116) @@ -129,5 +129,4 @@ ar5312GpioSetIntr(struct ath_hal *ah, u_int gpio, uint (void) ar5212SetInterrupts(ah, AH5212(ah)->ah_maskReg | HAL_INT_GPIO); } - #endif /* AH_SUPPORT_AR5312 */ Modified: head/sys/dev/ath/ath_hal/ar5312/ar5312_interrupts.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5312/ar5312_interrupts.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5312/ar5312_interrupts.c Tue Sep 1 21:41:07 2020 (r365116) @@ -29,7 +29,6 @@ #include "ar5312/ar5312reg.h" #include "ar5312/ar5312phy.h" - /* * Checks to see if an interrupt is pending on our NIC * Modified: head/sys/dev/ath/ath_hal/ar5312/ar5312_reset.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5312/ar5312_reset.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5312/ar5312_reset.c Tue Sep 1 21:41:07 2020 (r365116) @@ -271,7 +271,7 @@ ar5312Reset(struct ath_hal *ah, HAL_OPMODE opmode, /* Set the mute mask to the correct default */ OS_REG_WRITE(ah, AR_SEQ_MASK, 0x0000000F); } - + if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_3) { /* Clear reg to alllow RX_CLEAR line debug */ OS_REG_WRITE(ah, AR_PHY_BLUETOOTH, 0); @@ -827,12 +827,10 @@ ar5312MacReset(struct ath_hal *ah, unsigned int RCMask OS_REG_READ(ah, (AR5315_RSTIMER_BASE- ((uint32_t) ah->ah_sh) +AR5315_RESET)); - } else #endif { - switch(wlanNum) { case 0: resetBB = AR5312_RC_BB0_CRES | AR5312_RC_WBB0_RES; Modified: head/sys/dev/ath/ath_hal/ar5312/ar5312reg.h ============================================================================== --- head/sys/dev/ath/ath_hal/ar5312/ar5312reg.h Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5312/ar5312reg.h Tue Sep 1 21:41:07 2020 (r365116) @@ -29,7 +29,6 @@ /* Register base addresses for modules which are not wmac modules */ /* 531X has a fixed memory map */ - #define REG_WRITE(_reg,_val) *((volatile uint32_t *)(_reg)) = (_val); #define REG_READ(_reg) *((volatile uint32_t *)(_reg)) /* @@ -128,7 +127,6 @@ #define AR5312_RC_WBB0_RES 0x00004000 /* Warm reset to WBB0 */ #define AR5312_RC_WMAC1_RES 0x00020000 /* Warm reset to WMAC1 */ #define AR5312_RC_WBB1_RES 0x00040000 /* Warm reset to WBB */ - #define AR_RAD2112_SREV_MAJOR 0x40 /* 2112 Major Rev */ Modified: head/sys/dev/ath/ath_hal/ar5312/ar5315_gpio.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5312/ar5315_gpio.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5312/ar5315_gpio.c Tue Sep 1 21:41:07 2020 (r365116) @@ -128,5 +128,4 @@ ar5315GpioSetIntr(struct ath_hal *ah, u_int gpio, uint (void) ar5212SetInterrupts(ah, AH5212(ah)->ah_maskReg | HAL_INT_GPIO); } - #endif /* AH_SUPPORT_2316 || AH_SUPPORT_2317 */ Modified: head/sys/dev/ath/ath_hal/ar5416/ar2133.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5416/ar2133.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5416/ar2133.c Tue Sep 1 21:41:07 2020 (r365116) @@ -278,7 +278,7 @@ ar2133SetRfRegs(struct ath_hal *ah, const struct ieee8 /* Setup Bank 6 Write */ ath_hal_ini_bank_setup(priv->Bank6Data, &AH5416(ah)->ah_ini_bank6, modesIndex); - + /* Only the 5 or 2 GHz OB/DB need to be set for a mode */ if (IEEE80211_IS_CHAN_2GHZ(chan)) { HALDEBUG(ah, HAL_DEBUG_EEPROM, "%s: 2ghz: OB_2:%d, DB_2:%d\n", @@ -473,7 +473,6 @@ ar2133GetNoiseFloor(struct ath_hal *ah, int16_t nfarra "NF calibrated [ctl] [chain 1] is %d\n", nf); nfarray[1] = nf; - nf = MS(OS_REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR); if (nf & 0x100) nf = 0 - ((nf ^ 0x1ff) + 1); @@ -522,7 +521,7 @@ ar2133RfDetach(struct ath_hal *ah) ath_hal_free(ahp->ah_rfHal); ahp->ah_rfHal = AH_NULL; } - + /* * Allocate memory for analog bank scratch buffers * Scratch Buffer will be reinitialized every reset so no need to zero now Modified: head/sys/dev/ath/ath_hal/ar5416/ar5416_ani.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5416/ar5416_ani.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5416/ar5416_ani.c Tue Sep 1 21:41:07 2020 (r365116) @@ -223,7 +223,6 @@ ar5416AniControl(struct ath_hal *ah, HAL_ANI_CMD cmd, return AH_FALSE; } - switch (cmd) { case HAL_ANI_NOISE_IMMUNITY_LEVEL: { u_int level = param; @@ -727,7 +726,7 @@ ar5416AniLowerImmunity(struct ath_hal *ah) struct ath_hal_5212 *ahp = AH5212(ah); struct ar5212AniState *aniState; const struct ar5212AniParams *params; - + HALASSERT(ANI_ENA(ah)); aniState = ahp->ah_curani; Modified: head/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c Tue Sep 1 21:41:07 2020 (r365116) @@ -721,7 +721,6 @@ ar5416SpurMitigate(struct ath_hal *ah, const struct ie SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); OS_REG_WRITE(ah, AR_PHY_TIMING11, new); - /* * ============================================ * pilot mask 1 [31:0] = +6..-26, no 0 bin @@ -893,7 +892,7 @@ ar5416FillCapabilityInfo(struct ath_hal *ah) struct ath_hal_private *ahpriv = AH_PRIVATE(ah); HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; uint16_t val; - + /* Construct wireless mode from EEPROM */ pCap->halWirelessModes = 0; if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { Modified: head/sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5416/ar5416_beacon.c Tue Sep 1 21:41:07 2020 (r365116) @@ -155,7 +155,7 @@ ar5416SetStaBeaconTimers(struct ath_hal *ah, const HAL uint32_t nextTbtt, nextdtim,beaconintval, dtimperiod; HALASSERT(bs->bs_intval != 0); - + /* NB: no cfp setting since h/w automatically takes care */ OS_REG_WRITE(ah, AR_NEXT_TBTT, TU_TO_USEC(bs->bs_nexttbtt)); Modified: head/sys/dev/ath/ath_hal/ar5416/ar5416_cal.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5416/ar5416_cal.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5416/ar5416_cal.c Tue Sep 1 21:41:07 2020 (r365116) @@ -196,7 +196,6 @@ ar5416RunInitCals(struct ath_hal *ah, int init_cal_cou } #endif - /* * AGC calibration for the AR5416, AR9130, AR9160, AR9280. */ @@ -623,7 +622,6 @@ ar5416LoadNF(struct ath_hal *ah, const struct ieee8021 h = AH5416(ah)->ah_cal.nfCalHist; HALDEBUG(ah, HAL_DEBUG_NFCAL, "CCA: "); for (i = 0; i < AR5416_NUM_NF_READINGS; i ++) { - /* Don't write to EXT radio CCA registers unless in HT/40 mode */ /* XXX this check should really be cleaner! */ if (i > 2 && !IEEE80211_IS_CHAN_HT40(chan)) @@ -674,7 +672,6 @@ ar5416LoadNF(struct ath_hal *ah, const struct ieee8021 * of next noise floor calibration the baseband does. */ for (i = 0; i < AR5416_NUM_NF_READINGS; i ++) { - /* Don't write to EXT radio CCA registers unless in HT/40 mode */ /* XXX this check should really be cleaner! */ if (i > 2 && !IEEE80211_IS_CHAN_HT40(chan)) @@ -780,7 +777,6 @@ ar5416SanitizeNF(struct ath_hal *ah, int16_t *nf) } } } - /* * Read the NF and check it against the noise floor threshold Modified: head/sys/dev/ath/ath_hal/ar5416/ar5416_cal.h ============================================================================== --- head/sys/dev/ath/ath_hal/ar5416/ar5416_cal.h Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5416/ar5416_cal.h Tue Sep 1 21:41:07 2020 (r365116) @@ -20,7 +20,7 @@ */ #ifndef _ATH_AR5416_CAL_H_ #define _ATH_AR5416_CAL_H_ - + typedef enum { ADC_DC_INIT_CAL = 0x1, ADC_GAIN_CAL = 0x2, Modified: head/sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5416/ar5416_gpio.c Tue Sep 1 21:41:07 2020 (r365116) @@ -131,7 +131,7 @@ ar5416GpioCfgOutput(struct ath_hal *ah, uint32_t gpio, return AH_TRUE; #undef N } - + /* * Configure GPIO Input lines */ Modified: head/sys/dev/ath/ath_hal/ar5416/ar5416_power.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5416/ar5416_power.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5416/ar5416_power.c Tue Sep 1 21:41:07 2020 (r365116) @@ -114,7 +114,7 @@ static void ar5416SetPowerModeNetworkSleep(struct ath_hal *ah, int setChip) { OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); - + if (setChip) OS_REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN); } Modified: head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c Tue Sep 1 21:40:47 2020 (r365115) +++ head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c Tue Sep 1 21:41:07 2020 (r365116) @@ -386,7 +386,6 @@ ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode, AR_PCU_MISC_MODE2_ENABLE_AGGWEP); } - /* * disable seq number generation in hw */ @@ -606,7 +605,7 @@ ar5416InitDMA(struct ath_hal *ah) * Setup receive FIFO threshold to hold off TX activities */ OS_REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); - + /* * reduce the number of usable entries in PCU TXBUF to avoid * wrap around. @@ -645,7 +644,7 @@ ar5416InitBB(struct ath_hal *ah, const struct ieee8021 /* Activate the PHY (includes baseband activate and synthesizer on) */ OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); - + /* * If the AP starts the calibration before the base band timeout * completes we could get rx_clear false triggering. Add an @@ -1049,7 +1048,6 @@ ar5416WriteTxPowerRateRegisters(struct ath_hal *ah, #undef POW_SM } - /************************************************************** * ar5416SetTransmitPower * @@ -1096,7 +1094,7 @@ ar5416SetTransmitPower(struct ath_hal *ah, if (IS_EEP_MINOR_V2(ah)) { AH5416(ah)->ah_ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; } - + if (!ar5416SetPowerPerRateTable(ah, pEepData, chan, &AH5416(ah)->ah_ratesArray[0], cfgCtl, @@ -1525,7 +1523,7 @@ ar5416InitPLL(struct ath_hal *ah, const struct ieee802 pll |= SM(0xb, AR_RTC_PLL_DIV); } else pll |= SM(0xb, AR_RTC_PLL_DIV); - + OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); /* TODO: *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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