From owner-freebsd-hackers@freebsd.org Mon May 23 21:41:07 2016 Return-Path: Delivered-To: freebsd-hackers@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id D5BFFB4795E for ; Mon, 23 May 2016 21:41:07 +0000 (UTC) (envelope-from jhb@freebsd.org) Received: from bigwig.baldwin.cx (bigwig.baldwin.cx [IPv6:2001:470:1f11:75::1]) (using TLSv1 with cipher DHE-RSA-CAMELLIA256-SHA (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id B670B12A3; Mon, 23 May 2016 21:41:07 +0000 (UTC) (envelope-from jhb@freebsd.org) Received: from ralph.baldwin.cx (c-73-231-226-104.hsd1.ca.comcast.net [73.231.226.104]) by bigwig.baldwin.cx (Postfix) with ESMTPSA id D2CACB9A8; Mon, 23 May 2016 17:41:06 -0400 (EDT) From: John Baldwin To: freebsd-hackers@freebsd.org Cc: Andriy Gapon , FreeBSD Hackers Subject: Re: hpet as nmi watchdog Date: Mon, 23 May 2016 13:44:55 -0700 Message-ID: <2056148.ZvOkyra82H@ralph.baldwin.cx> User-Agent: KMail/4.14.3 (FreeBSD/10.2-STABLE; KDE/4.14.3; amd64; ; ) In-Reply-To: <56DEB97D.2010804@FreeBSD.org> References: <56DEB97D.2010804@FreeBSD.org> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.2.7 (bigwig.baldwin.cx); Mon, 23 May 2016 17:41:06 -0400 (EDT) X-BeenThere: freebsd-hackers@freebsd.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: Technical Discussions relating to FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 May 2016 21:41:08 -0000 On Tuesday, March 08, 2016 01:37:33 PM Andriy Gapon wrote: > > I toyed a little bit with an idea of using a HPET timer as an NMI watchdog. > The idea is that a HPET timer is somehow configured to generate an NMI when it > fires. The timer normally would not fire, of course, as it is constantly being > reprogrammed to some future time as is the case for all watchdogs. > > I have written some proof of concept code using two approaches. One approach is > to use the "FSB" (MSI-like) mode of a HPET timer and program a corresponding FSB > data register (HPET_TIMER_FSB_VAL) with a value that sets NMI delivery mode > using the IO-APIC specification. The other approach is to use legacy interrupt > mode for the HPET timer and program a corresponding IO-APIC pin for NMI deliver > mode. > In both cases I haven't got a desired result - instead of an NMI a test system > gets reset when the timer fires. I wonder if this is a quirk of my old hardware > (HPET in AMD SB7xx, family 10h processor) or if my idea is a non-starter. This is an interesting idea. You could also use one of the other timers (8254, etc.) as a watchdog by setting the I/O APIC pin to NMI as well. It maybe that for the MSI case the chipset treats the NMI delivery mode as an error, hence the reset. :-/ -- John Baldwin