From owner-svn-src-head@freebsd.org Mon May 1 19:47:12 2017 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 6186ED59468; Mon, 1 May 2017 19:47:12 +0000 (UTC) (envelope-from mav@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 0CF6A218; Mon, 1 May 2017 19:47:11 +0000 (UTC) (envelope-from mav@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id v41JlBcR031964; Mon, 1 May 2017 19:47:11 GMT (envelope-from mav@FreeBSD.org) Received: (from mav@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id v41JlAIv031962; Mon, 1 May 2017 19:47:10 GMT (envelope-from mav@FreeBSD.org) Message-Id: <201705011947.v41JlAIv031962@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: mav set sender to mav@FreeBSD.org using -f From: Alexander Motin Date: Mon, 1 May 2017 19:47:10 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r317659 - head/sys/dev/uart X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 01 May 2017 19:47:12 -0000 Author: mav Date: Mon May 1 19:47:10 2017 New Revision: 317659 URL: https://svnweb.freebsd.org/changeset/base/317659 Log: Make some UART consoles to not spin wait for data to be sent. At least with Tx FIFO enabled it shows me ~10% reduction of verbose boot time with serial console at 115200 baud. Reviewed by: marcel MFC after: 2 weeks Modified: head/sys/dev/uart/uart_dev_lpc.c head/sys/dev/uart/uart_dev_ns8250.c Modified: head/sys/dev/uart/uart_dev_lpc.c ============================================================================== --- head/sys/dev/uart/uart_dev_lpc.c Mon May 1 19:34:15 2017 (r317658) +++ head/sys/dev/uart/uart_dev_lpc.c Mon May 1 19:47:10 2017 (r317659) @@ -345,9 +345,6 @@ lpc_ns8250_putc(struct uart_bas *bas, in DELAY(4); uart_setreg(bas, REG_DATA, c); uart_barrier(bas); - limit = 250000; - while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) - DELAY(4); } static int @@ -890,8 +887,13 @@ lpc_ns8250_bus_transmit(struct uart_soft bas = &sc->sc_bas; uart_lock(sc->sc_hwmtx); - while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) - ; + if (sc->sc_txdatasz > 1) { + if ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0) + ns8250_drain(bas, UART_DRAIN_TRANSMITTER); + } else { + while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) + DELAY(4); + } for (i = 0; i < sc->sc_txdatasz; i++) { uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); uart_barrier(bas); Modified: head/sys/dev/uart/uart_dev_ns8250.c ============================================================================== --- head/sys/dev/uart/uart_dev_ns8250.c Mon May 1 19:34:15 2017 (r317658) +++ head/sys/dev/uart/uart_dev_ns8250.c Mon May 1 19:47:10 2017 (r317659) @@ -315,7 +315,7 @@ ns8250_init(struct uart_bas *bas, int ba /* Disable the FIFO (if present). */ val = 0; #ifdef CPU_XBURST - val = FCR_UART_ON; + val |= FCR_UART_ON; #endif uart_setreg(bas, REG_FCR, val); uart_barrier(bas); @@ -346,9 +346,6 @@ ns8250_putc(struct uart_bas *bas, int c) DELAY(4); uart_setreg(bas, REG_DATA, c); uart_barrier(bas); - limit = 250000; - while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) - DELAY(4); } static int @@ -999,8 +996,13 @@ ns8250_bus_transmit(struct uart_softc *s bas = &sc->sc_bas; uart_lock(sc->sc_hwmtx); - while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) - ; + if (sc->sc_txdatasz > 1) { + if ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0) + ns8250_drain(bas, UART_DRAIN_TRANSMITTER); + } else { + while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) + DELAY(4); + } for (i = 0; i < sc->sc_txdatasz; i++) { uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); uart_barrier(bas);