From owner-svn-src-all@freebsd.org Fri Nov 16 23:39:41 2018 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 694F21107DFE; Fri, 16 Nov 2018 23:39:41 +0000 (UTC) (envelope-from jhb@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 1091B6E987; Fri, 16 Nov 2018 23:39:41 +0000 (UTC) (envelope-from jhb@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id E5C7A2404A; Fri, 16 Nov 2018 23:39:40 +0000 (UTC) (envelope-from jhb@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id wAGNdeIB014096; Fri, 16 Nov 2018 23:39:40 GMT (envelope-from jhb@FreeBSD.org) Received: (from jhb@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id wAGNdeVE014093; Fri, 16 Nov 2018 23:39:40 GMT (envelope-from jhb@FreeBSD.org) Message-Id: <201811162339.wAGNdeVE014093@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: jhb set sender to jhb@FreeBSD.org using -f From: John Baldwin Date: Fri, 16 Nov 2018 23:39:40 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r340488 - in head/sys/x86: include x86 xen X-SVN-Group: head X-SVN-Commit-Author: jhb X-SVN-Commit-Paths: in head/sys/x86: include x86 xen X-SVN-Commit-Revision: 340488 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: 1091B6E987 X-Spamd-Result: default: False [0.00 / 15.00]; local_wl_from(0.00)[FreeBSD.org] X-Rspamd-Server: mx1.freebsd.org X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 16 Nov 2018 23:39:41 -0000 Author: jhb Date: Fri Nov 16 23:39:39 2018 New Revision: 340488 URL: https://svnweb.freebsd.org/changeset/base/340488 Log: Axe MINIMUM_MSI_INT. Just allow MSI interrupts to always start at the end of the I/O APIC pins. Since existing machines already have more than 255 I/O APIC pins, IRQ 255 is no longer reliably invalid, so just remove the minimum starting value for MSI. Reviewed by: kib, markj Differential Revision: https://reviews.freebsd.org/D17991 Modified: head/sys/x86/include/intr_machdep.h head/sys/x86/x86/msi.c head/sys/x86/xen/pvcpu_enum.c head/sys/x86/xen/xen_msi.c Modified: head/sys/x86/include/intr_machdep.h ============================================================================== --- head/sys/x86/include/intr_machdep.h Fri Nov 16 21:27:11 2018 (r340487) +++ head/sys/x86/include/intr_machdep.h Fri Nov 16 23:39:39 2018 (r340488) @@ -51,15 +51,11 @@ * IRQ values returned by ACPI methods such as _CRS can be used * directly by the ACPI bus driver. * - * MSI interrupts allocate a block of interrupts starting at either - * the end of the I/O APIC range or 256, whichever is higher. When - * running under the Xen Hypervisor, an additional range of IRQ values - * are available for binding to event channel events. We use 256 as - * the minimum IRQ value for MSI interrupts to attempt to leave 255 - * unused since 255 is used in PCI to indicate an invalid INTx IRQ. + * MSI interrupts allocate a block of interrupts starting at the end + * of the I/O APIC range. When running under the Xen Hypervisor, an + * additional range of IRQ values are available for binding to event + * channel events. */ -#define MINIMUM_MSI_INT 256 - extern u_int first_msi_irq; extern u_int num_io_irqs; extern u_int num_msi_irqs; Modified: head/sys/x86/x86/msi.c ============================================================================== --- head/sys/x86/x86/msi.c Fri Nov 16 21:27:11 2018 (r340487) +++ head/sys/x86/x86/msi.c Fri Nov 16 23:39:39 2018 (r340488) @@ -153,6 +153,8 @@ struct pic msi_pic = { }; u_int first_msi_irq; +SYSCTL_UINT(_machdep, OID_AUTO, first_msi_irq, CTLFLAG_RD, &first_msi_irq, 0, + "Number of first IRQ reserved for MSI and MSI-X interrupts"); u_int num_msi_irqs = 512; SYSCTL_UINT(_machdep, OID_AUTO, num_msi_irqs, CTLFLAG_RDTUN, &num_msi_irqs, 0, @@ -339,7 +341,7 @@ msi_init(void) if (num_msi_irqs == 0) return; - first_msi_irq = max(MINIMUM_MSI_INT, num_io_irqs); + first_msi_irq = num_io_irqs; if (num_msi_irqs > UINT_MAX - first_msi_irq) panic("num_msi_irq too high"); num_io_irqs = first_msi_irq + num_msi_irqs; Modified: head/sys/x86/xen/pvcpu_enum.c ============================================================================== --- head/sys/x86/xen/pvcpu_enum.c Fri Nov 16 21:27:11 2018 (r340487) +++ head/sys/x86/xen/pvcpu_enum.c Fri Nov 16 23:39:39 2018 (r340488) @@ -199,7 +199,7 @@ xenpv_setup_io(void) * this is legacy code so just keep using the previous * behaviour and assume a maximum of 256 interrupts. */ - num_io_irqs = max(MINIMUM_MSI_INT - 1, num_io_irqs); + num_io_irqs = max(255, num_io_irqs); acpi_SetDefaultIntrModel(ACPI_INTR_APIC); } Modified: head/sys/x86/xen/xen_msi.c ============================================================================== --- head/sys/x86/xen/xen_msi.c Fri Nov 16 21:27:11 2018 (r340487) +++ head/sys/x86/xen/xen_msi.c Fri Nov 16 23:39:39 2018 (r340488) @@ -57,7 +57,7 @@ xen_msi_init(void) { MPASS(num_io_irqs > 0); - first_msi_irq = min(MINIMUM_MSI_INT, num_io_irqs); + first_msi_irq = num_io_irqs; if (num_msi_irqs > UINT_MAX - first_msi_irq) panic("num_msi_irq too high"); num_io_irqs = first_msi_irq + num_msi_irqs;