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From: "Randall R. Stewart" <rrs@FreeBSD.org>
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Subject: PERFORCE change 136428 for review
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http://perforce.freebsd.org/chv.cgi?CH=136428

Change 136428 by rrs@rrs-mips2-jnpr on 2008/02/28 13:53:09

	make sure the right mask is in place in all SR sets.

Affected files ...

.. //depot/projects/mips2-jnpr/src/sys/mips/mips/vm_machdep.c#21 edit

Differences ...

==== //depot/projects/mips2-jnpr/src/sys/mips/mips/vm_machdep.c#21 (text+ko) ====

@@ -148,7 +148,7 @@
 	pcb2->pcb_context.val[PCB_REG_S0] = (register_t)fork_return;
 	pcb2->pcb_context.val[PCB_REG_S1] = (register_t)td2;
 	pcb2->pcb_context.val[PCB_REG_S2] = (register_t)td2->td_frame;
-	pcb2->pcb_context.val[PCB_REG_SR] = SR_INT_MASK;   /* SR */
+	pcb2->pcb_context.val[PCB_REG_SR] = SR_INT_MASK;
 	/*
 	 * FREEBSD_DEVELOPERS_FIXME:
 	 * Setup any other CPU-Specific registers (Not MIPS Standard)
@@ -302,7 +302,7 @@
 
 	/* Dont set IE bit in SR. sched lock release will take care of it */
 /* idle_mask is jmips pcb2->pcb_context.val[11] = (ALL_INT_MASK & idle_mask); */
-	pcb2->pcb_context.val[PCB_REG_SR] = 0;
+	pcb2->pcb_context.val[PCB_REG_SR] = SR_INT_MASK;
 #ifdef TARGET_OCTEON
 	pcb2->pcb_context.val[PCB_REG_SR] |= MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT |
 	  MIPS32_SR_PX | MIPS_SR_UX | MIPS_SR_KX | MIPS_SR_SX;