Date: Sat, 28 Jul 2018 07:54:21 +0000 (UTC) From: Andrew Turner <andrew@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r336806 - in head/sys: arm/arm arm/include conf Message-ID: <201807280754.w6S7sLY3036012@repo.freebsd.org>
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Author: andrew Date: Sat Jul 28 07:54:21 2018 New Revision: 336806 URL: https://svnweb.freebsd.org/changeset/base/336806 Log: Only support INTRNG in the SMP code on arm. We already require INTRNG on anything that could be multicore on arm. Modified: head/sys/arm/arm/mp_machdep.c head/sys/arm/include/smp.h head/sys/conf/options.arm Modified: head/sys/arm/arm/mp_machdep.c ============================================================================== --- head/sys/arm/arm/mp_machdep.c Sat Jul 28 07:37:01 2018 (r336805) +++ head/sys/arm/arm/mp_machdep.c Sat Jul 28 07:54:21 2018 (r336806) @@ -26,7 +26,6 @@ * SUCH DAMAGE. */ #include "opt_ddb.h" -#include "opt_smp.h" #include <sys/cdefs.h> __FBSDID("$FreeBSD$"); @@ -75,9 +74,6 @@ volatile int mp_naps; /* Set to 1 once we're ready to let the APs out of the pen. */ volatile int aps_ready = 0; -#ifndef INTRNG -static int ipi_handler(void *arg); -#endif void set_stackptrs(int cpu); /* Temporary variables for init_secondary() */ @@ -153,9 +149,6 @@ init_secondary(int cpu) { struct pcpu *pc; uint32_t loop_counter; -#ifndef INTRNG - int start = 0, end = 0; -#endif pmap_set_tex(); cpuinfo_reinit_mmu(pmap_kern_ttb); @@ -215,20 +208,6 @@ init_secondary(int cpu) mtx_unlock_spin(&ap_boot_mtx); -#ifndef INTRNG - /* Enable ipi */ -#ifdef IPI_IRQ_START - start = IPI_IRQ_START; -#ifdef IPI_IRQ_END - end = IPI_IRQ_END; -#else - end = IPI_IRQ_START; -#endif -#endif - - for (int i = start; i <= end; i++) - arm_unmask_irq(i); -#endif /* INTRNG */ enable_interrupts(PSR_I); loop_counter = 0; @@ -250,7 +229,6 @@ init_secondary(int cpu) /* NOTREACHED */ } -#ifdef INTRNG static void ipi_rendezvous(void *dummy __unused) { @@ -347,126 +325,20 @@ ipi_hardclock(void *arg) critical_exit(); } -#else -static int -ipi_handler(void *arg) -{ - u_int cpu, ipi; - - cpu = PCPU_GET(cpuid); - - ipi = pic_ipi_read((int)arg); - - while ((ipi != 0x3ff)) { - switch (ipi) { - case IPI_RENDEZVOUS: - CTR0(KTR_SMP, "IPI_RENDEZVOUS"); - smp_rendezvous_action(); - break; - - case IPI_AST: - CTR0(KTR_SMP, "IPI_AST"); - break; - - case IPI_STOP: - /* - * IPI_STOP_HARD is mapped to IPI_STOP so it is not - * necessary to add it in the switch. - */ - CTR0(KTR_SMP, "IPI_STOP or IPI_STOP_HARD"); - - savectx(&stoppcbs[cpu]); - - /* - * CPUs are stopped when entering the debugger and at - * system shutdown, both events which can precede a - * panic dump. For the dump to be correct, all caches - * must be flushed and invalidated, but on ARM there's - * no way to broadcast a wbinv_all to other cores. - * Instead, we have each core do the local wbinv_all as - * part of stopping the core. The core requesting the - * stop will do the l2 cache flush after all other cores - * have done their l1 flushes and stopped. - */ - dcache_wbinv_poc_all(); - - /* Indicate we are stopped */ - CPU_SET_ATOMIC(cpu, &stopped_cpus); - - /* Wait for restart */ - while (!CPU_ISSET(cpu, &started_cpus)) - cpu_spinwait(); - - CPU_CLR_ATOMIC(cpu, &started_cpus); - CPU_CLR_ATOMIC(cpu, &stopped_cpus); -#ifdef DDB - dbg_resume_dbreg(); -#endif - CTR0(KTR_SMP, "IPI_STOP (restart)"); - break; - case IPI_PREEMPT: - CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__); - sched_preempt(curthread); - break; - case IPI_HARDCLOCK: - CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__); - hardclockintr(); - break; - default: - panic("Unknown IPI 0x%0x on cpu %d", ipi, curcpu); - } - - pic_ipi_clear(ipi); - ipi = pic_ipi_read(-1); - } - - return (FILTER_HANDLED); -} -#endif - static void release_aps(void *dummy __unused) { uint32_t loop_counter; -#ifndef INTRNG - int start = 0, end = 0; -#endif if (mp_ncpus == 1) return; -#ifdef INTRNG intr_pic_ipi_setup(IPI_RENDEZVOUS, "rendezvous", ipi_rendezvous, NULL); intr_pic_ipi_setup(IPI_AST, "ast", ipi_ast, NULL); intr_pic_ipi_setup(IPI_STOP, "stop", ipi_stop, NULL); intr_pic_ipi_setup(IPI_PREEMPT, "preempt", ipi_preempt, NULL); intr_pic_ipi_setup(IPI_HARDCLOCK, "hardclock", ipi_hardclock, NULL); -#else -#ifdef IPI_IRQ_START - start = IPI_IRQ_START; -#ifdef IPI_IRQ_END - end = IPI_IRQ_END; -#else - end = IPI_IRQ_START; -#endif -#endif - for (int i = start; i <= end; i++) { - /* - * IPI handler - */ - /* - * Use 0xdeadbeef as the argument value for irq 0, - * if we used 0, the intr code will give the trap frame - * pointer instead. - */ - arm_setup_irqhandler("ipi", ipi_handler, NULL, (void *)i, i, - INTR_TYPE_MISC | INTR_EXCL, NULL); - - /* Enable ipi */ - arm_unmask_irq(i); - } -#endif atomic_store_rel_int(&aps_ready, 1); /* Wake the other threads up */ dsb(); @@ -507,11 +379,7 @@ ipi_all_but_self(u_int ipi) other_cpus = all_cpus; CPU_CLR(PCPU_GET(cpuid), &other_cpus); CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); -#ifdef INTRNG intr_ipi_send(other_cpus, ipi); -#else - pic_ipi_send(other_cpus, ipi); -#endif } void @@ -523,11 +391,7 @@ ipi_cpu(int cpu, u_int ipi) CPU_SET(cpu, &cpus); CTR3(KTR_SMP, "%s: cpu: %d, ipi: %x", __func__, cpu, ipi); -#ifdef INTRNG intr_ipi_send(cpus, ipi); -#else - pic_ipi_send(cpus, ipi); -#endif } void @@ -535,9 +399,5 @@ ipi_selected(cpuset_t cpus, u_int ipi) { CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); -#ifdef INTRNG intr_ipi_send(cpus, ipi); -#else - pic_ipi_send(cpus, ipi); -#endif } Modified: head/sys/arm/include/smp.h ============================================================================== --- head/sys/arm/include/smp.h Sat Jul 28 07:37:01 2018 (r336805) +++ head/sys/arm/include/smp.h Sat Jul 28 07:54:21 2018 (r336806) @@ -6,7 +6,6 @@ #include <sys/_cpuset.h> #include <machine/pcb.h> -#ifdef INTRNG enum { IPI_AST, IPI_PREEMPT, @@ -18,16 +17,6 @@ enum { IPI_CACHE, /* Not used now, but keep it reserved. */ INTR_IPI_COUNT }; -#else -#define IPI_AST 0 -#define IPI_PREEMPT 2 -#define IPI_RENDEZVOUS 3 -#define IPI_STOP 4 -#define IPI_STOP_HARD 4 -#define IPI_HARDCLOCK 6 -#define IPI_TLB 7 /* Not used now, but keep it reserved. */ -#define IPI_CACHE 8 /* Not used now, but keep it reserved. */ -#endif /* INTRNG */ void init_secondary(int cpu); void mpentry(void); @@ -35,13 +24,6 @@ void mpentry(void); void ipi_all_but_self(u_int ipi); void ipi_cpu(int cpu, u_int ipi); void ipi_selected(cpuset_t cpus, u_int ipi); - -/* PIC interface */ -#ifndef INTRNG -void pic_ipi_send(cpuset_t cpus, u_int ipi); -void pic_ipi_clear(int ipi); -int pic_ipi_read(int arg); -#endif /* Platform interface */ void platform_mp_setmaxid(void); Modified: head/sys/conf/options.arm ============================================================================== --- head/sys/conf/options.arm Sat Jul 28 07:37:01 2018 (r336805) +++ head/sys/conf/options.arm Sat Jul 28 07:54:21 2018 (r336806) @@ -23,8 +23,6 @@ EFI opt_platform.h FLASHADDR opt_global.h GIC_DEFAULT_ICFGR_INIT opt_global.h INTRNG opt_global.h -IPI_IRQ_START opt_smp.h -IPI_IRQ_END opt_smp.h FREEBSD_BOOT_LOADER opt_global.h KERNBASE opt_global.h KERNVIRTADDR opt_global.h
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