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From: Jung-uk Kim <jkim@FreeBSD.org>
Date: Fri, 4 Mar 2011 23:43:10 +0000 (UTC)
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Subject: svn commit: r219279 - stable/7/sys/i386/cpufreq
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Author: jkim
Date: Fri Mar  4 23:43:10 2011
New Revision: 219279
URL: http://svn.freebsd.org/changeset/base/219279

Log:
  MFC:	r219046
  
  Set C1 "I/O then Halt" capability bit for Intel EIST.  Some broken BIOSes
  refuse to load external SSDTs if this bit is unset for _PDC.

Modified:
  stable/7/sys/i386/cpufreq/est.c

Modified: stable/7/sys/i386/cpufreq/est.c
==============================================================================
--- stable/7/sys/i386/cpufreq/est.c	Fri Mar  4 23:12:14 2011	(r219278)
+++ stable/7/sys/i386/cpufreq/est.c	Fri Mar  4 23:43:10 2011	(r219279)
@@ -942,8 +942,11 @@ static int
 est_features(driver_t *driver, u_int *features)
 {
 
-	/* Notify the ACPI CPU that we support direct access to MSRs */
-	*features = ACPI_CAP_PERF_MSRS;
+	/*
+	 * Notify the ACPI CPU that we support direct access to MSRs.
+	 * XXX C1 "I/O then Halt" seems necessary for some broken BIOS.
+	 */
+	*features = ACPI_CAP_PERF_MSRS | ACPI_CAP_C1_IO_HALT;
 	return (0);
 }