From owner-freebsd-current Tue Jan 30 10:40:56 1996 Return-Path: owner-current Received: (from root@localhost) by freefall.freebsd.org (8.7.3/8.7.3) id KAA15715 for current-outgoing; Tue, 30 Jan 1996 10:40:56 -0800 (PST) Received: from ormail.intel.com ([134.134.192.3]) by freefall.freebsd.org (8.7.3/8.7.3) with SMTP id KAA15642 Tue, 30 Jan 1996 10:40:28 -0800 (PST) Received: from ichips.intel.com (ichips.intel.com [134.134.50.200]) by ormail.intel.com (8.6.12/8.6.12) with ESMTP id KAA18905; Tue, 30 Jan 1996 10:37:56 -0800 Received: from pdxlx008.intel.com.intel.com by ichips.intel.com (8.7.1/jIII); Tue, 30 Jan 1996 10:37:54 -0800 (PST) Received: from loopback.jf.intel.com by pdxlx008.intel.com.intel.com (8.6.12/10.0i); Tue, 30 Jan 1996 10:37:55 -0800 Message-Id: <199601301837.KAA07469@pdxlx008.intel.com.intel.com> To: Bruce Evans cc: terry@lambert.org, current@freefall.freebsd.org, dyson@freefall.freebsd.org Subject: Re: Optimization topics In-reply-to: Your message of "Tue, 30 Jan 1996 15:08:25 +1100." <199601300408.PAA18640@godzilla.zeta.org.au> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Date: Tue, 30 Jan 1996 10:37:55 -0800 From: Wayne Scott Sender: owner-current@FreeBSD.ORG Precedence: bulk > >Specifically, it should be possible to run FreeBSD with the unaligned > >access bit set to disallow unaligned access of word/dword/qword objects. > > I implemented this in Minix about 5 years ago. My compiler generates > many misaligned access (it forgets to align switch tables) and gcc > generates a few (e.g., it generates pessimized inline code for assigning > poorly (but correctly!) aligned structs: I might have an easier solution for you. The Pentium Pro has a misaligned access performance counter that has the ability to generate interrupts. You can tell the processor to count misaligns and generate an interrupt every 1000 times it sees one. Put this into you existing profiling code and you will get a profile of where the system is doing misaligned references. Now you only need to fix the very common cases in the critical paths. The same thing can be done which all the counters. Which branches are not predicted well, where am I missing the cache, etc... The information is in the P6 PRM that should be available next month... -Wayne Wayne Scott P6 Architecture wscott@ichips.intel.com Work #: (503) 264-4165 Disclaimer: All views expressed are my own opinions, and not necessarily those of Intel Corporation.