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From: Dimitry Andric
Date: Thu, 3 May 2012 16:50:56 +0000 (UTC)
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Subject: svn commit: r234971 - in vendor/llvm/dist: . autoconf cmake/modules
docs docs/CommandGuide include/llvm include/llvm-c
include/llvm/ADT include/llvm/CodeGen include/llvm/Config
include/llvm/MC/MCPa...
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Author: dim
Date: Thu May 3 16:50:55 2012
New Revision: 234971
URL: http://svn.freebsd.org/changeset/base/234971
Log:
Vendor import of llvm release_31 branch r155985:
http://llvm.org/svn/llvm-project/llvm/branches/release_31@155985
Added:
vendor/llvm/dist/include/llvm/Support/Locale.h
vendor/llvm/dist/include/llvm/Support/MDBuilder.h
vendor/llvm/dist/lib/ExecutionEngine/RuntimeDyld/GDBRegistrar.cpp
vendor/llvm/dist/lib/ExecutionEngine/RuntimeDyld/JITRegistrar.h
vendor/llvm/dist/lib/ExecutionEngine/RuntimeDyld/ObjectImage.h
vendor/llvm/dist/lib/Support/Locale.cpp
vendor/llvm/dist/lib/Support/LocaleGeneric.inc
vendor/llvm/dist/lib/Support/LocaleWindows.inc
vendor/llvm/dist/lib/Support/LocaleXlocale.inc
vendor/llvm/dist/lib/Target/Mips/Disassembler/
vendor/llvm/dist/lib/Target/Mips/Disassembler/CMakeLists.txt
vendor/llvm/dist/lib/Target/Mips/Disassembler/LLVMBuild.txt
vendor/llvm/dist/lib/Target/Mips/Disassembler/Makefile
vendor/llvm/dist/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
vendor/llvm/dist/test/CodeGen/PowerPC/ppc-vaarg-agg.ll
vendor/llvm/dist/test/CodeGen/X86/2012-04-26-sdglue.ll
vendor/llvm/dist/test/CodeGen/X86/GC/cg-O0.ll
vendor/llvm/dist/test/CodeGen/X86/avx2-vperm.ll (contents, props changed)
vendor/llvm/dist/test/CodeGen/X86/dbg-declare.ll
vendor/llvm/dist/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt
vendor/llvm/dist/test/MC/Disassembler/ARM/unpredictable-AI1cmp-arm.txt
vendor/llvm/dist/test/MC/Disassembler/ARM/unpredictable-MRRC2-arm.txt
vendor/llvm/dist/test/MC/Disassembler/ARM/unpredictable-MRS-arm.txt
vendor/llvm/dist/test/MC/Disassembler/ARM/unpredictable-swp-arm.txt
vendor/llvm/dist/test/MC/Disassembler/Mips/
vendor/llvm/dist/test/MC/Disassembler/Mips/mips32.txt
vendor/llvm/dist/test/MC/Disassembler/Mips/mips32_le.txt
vendor/llvm/dist/test/MC/Disassembler/Mips/mips32r2.txt
vendor/llvm/dist/test/MC/Disassembler/Mips/mips32r2_le.txt
vendor/llvm/dist/test/MC/Disassembler/Mips/mips64.txt
vendor/llvm/dist/test/MC/Disassembler/Mips/mips64_le.txt
vendor/llvm/dist/test/MC/Disassembler/Mips/mips64r2.txt
vendor/llvm/dist/test/MC/Disassembler/Mips/mips64r2_le.txt
vendor/llvm/dist/test/MC/Mips/sym-offset.ll
vendor/llvm/dist/test/Transforms/BBVectorize/no-ldstr-conn.ll
vendor/llvm/dist/test/Transforms/BBVectorize/simple-ldstr-ptrs.ll
vendor/llvm/dist/test/Transforms/BBVectorize/simple-sel.ll
vendor/llvm/dist/test/Transforms/InstCombine/2012-04-30-SRem.ll
vendor/llvm/dist/test/Transforms/LoopStrengthReduce/pr12691.ll
vendor/llvm/dist/test/Transforms/LoopUnswitch/2012-04-30-LoopUnswitch-LPad-Crash.ll
vendor/llvm/dist/test/Transforms/ObjCARC/escape.ll
vendor/llvm/dist/test/Transforms/Reassociate/pr12245.ll
vendor/llvm/dist/test/Transforms/SimplifyLibCalls/win-math.ll
vendor/llvm/dist/test/Verifier/fpmath.ll
vendor/llvm/dist/unittests/Support/MDBuilderTest.cpp
Deleted:
vendor/llvm/dist/include/llvm/Support/JSONParser.h
vendor/llvm/dist/lib/Support/JSONParser.cpp
vendor/llvm/dist/lib/Target/Hexagon/HexagonMCInst.h
vendor/llvm/dist/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
vendor/llvm/dist/test/CodeGen/Generic/dbg-declare.ll
vendor/llvm/dist/test/Verifier/fpaccuracy.ll
vendor/llvm/dist/unittests/Support/JSONParserTest.cpp
vendor/llvm/dist/utils/json-bench/
Modified:
vendor/llvm/dist/CMakeLists.txt
vendor/llvm/dist/CREDITS.TXT
vendor/llvm/dist/autoconf/configure.ac
vendor/llvm/dist/cmake/modules/HandleLLVMOptions.cmake
vendor/llvm/dist/configure
vendor/llvm/dist/docs/CodeGenerator.html
vendor/llvm/dist/docs/CommandGuide/FileCheck.pod
vendor/llvm/dist/docs/DebuggingJITedCode.html
vendor/llvm/dist/docs/LLVMBuild.html
vendor/llvm/dist/docs/LangRef.html
vendor/llvm/dist/docs/ProgrammersManual.html
vendor/llvm/dist/docs/ReleaseNotes.html
vendor/llvm/dist/docs/TestingGuide.html
vendor/llvm/dist/include/llvm-c/lto.h
vendor/llvm/dist/include/llvm/ADT/SmallPtrSet.h
vendor/llvm/dist/include/llvm/ADT/StringMap.h
vendor/llvm/dist/include/llvm/CodeGen/DFAPacketizer.h
vendor/llvm/dist/include/llvm/CodeGen/Passes.h
vendor/llvm/dist/include/llvm/CodeGen/ScheduleDAGInstrs.h
vendor/llvm/dist/include/llvm/CodeGen/SlotIndexes.h
vendor/llvm/dist/include/llvm/Config/config.h.cmake
vendor/llvm/dist/include/llvm/Config/config.h.in
vendor/llvm/dist/include/llvm/IntrinsicsX86.td
vendor/llvm/dist/include/llvm/LLVMContext.h
vendor/llvm/dist/include/llvm/MC/MCParser/AsmLexer.h
vendor/llvm/dist/include/llvm/MC/MCParser/MCAsmLexer.h
vendor/llvm/dist/include/llvm/Object/ELF.h
vendor/llvm/dist/include/llvm/Operator.h
vendor/llvm/dist/include/llvm/Support/IRBuilder.h
vendor/llvm/dist/include/llvm/Support/Process.h
vendor/llvm/dist/include/llvm/Support/SourceMgr.h
vendor/llvm/dist/include/llvm/Support/YAMLParser.h
vendor/llvm/dist/include/llvm/Support/raw_ostream.h
vendor/llvm/dist/include/llvm/TableGen/Error.h
vendor/llvm/dist/include/llvm/TableGen/Record.h
vendor/llvm/dist/include/llvm/Target/TargetLibraryInfo.h
vendor/llvm/dist/include/llvm/Target/TargetRegisterInfo.h
vendor/llvm/dist/include/llvm/Transforms/Utils/BasicBlockUtils.h
vendor/llvm/dist/include/llvm/Transforms/Vectorize.h
vendor/llvm/dist/lib/Analysis/ConstantFolding.cpp
vendor/llvm/dist/lib/Analysis/ScalarEvolution.cpp
vendor/llvm/dist/lib/Analysis/ValueTracking.cpp
vendor/llvm/dist/lib/CodeGen/AsmPrinter/DwarfAccelTable.cpp
vendor/llvm/dist/lib/CodeGen/AsmPrinter/DwarfAccelTable.h
vendor/llvm/dist/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
vendor/llvm/dist/lib/CodeGen/DFAPacketizer.cpp
vendor/llvm/dist/lib/CodeGen/LiveIntervalAnalysis.cpp
vendor/llvm/dist/lib/CodeGen/MachineBasicBlock.cpp
vendor/llvm/dist/lib/CodeGen/MachineBlockPlacement.cpp
vendor/llvm/dist/lib/CodeGen/Passes.cpp
vendor/llvm/dist/lib/CodeGen/ScheduleDAGInstrs.cpp
vendor/llvm/dist/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
vendor/llvm/dist/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
vendor/llvm/dist/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
vendor/llvm/dist/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
vendor/llvm/dist/lib/CodeGen/SelectionDAG/TargetLowering.cpp
vendor/llvm/dist/lib/CodeGen/SlotIndexes.cpp
vendor/llvm/dist/lib/ExecutionEngine/RuntimeDyld/CMakeLists.txt
vendor/llvm/dist/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp
vendor/llvm/dist/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
vendor/llvm/dist/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.h
vendor/llvm/dist/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldImpl.h
vendor/llvm/dist/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.cpp
vendor/llvm/dist/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.h
vendor/llvm/dist/lib/MC/MCParser/AsmParser.cpp
vendor/llvm/dist/lib/Object/ELFObjectFile.cpp
vendor/llvm/dist/lib/Support/CMakeLists.txt
vendor/llvm/dist/lib/Support/SmallPtrSet.cpp
vendor/llvm/dist/lib/Support/SourceMgr.cpp
vendor/llvm/dist/lib/Support/Unix/Process.inc
vendor/llvm/dist/lib/Support/Windows/Process.inc
vendor/llvm/dist/lib/Support/YAMLParser.cpp
vendor/llvm/dist/lib/Support/raw_ostream.cpp
vendor/llvm/dist/lib/TableGen/Error.cpp
vendor/llvm/dist/lib/Target/ARM/ARMCallingConv.td
vendor/llvm/dist/lib/Target/ARM/ARMInstrFormats.td
vendor/llvm/dist/lib/Target/ARM/ARMInstrInfo.td
vendor/llvm/dist/lib/Target/ARM/ARMInstrNEON.td
vendor/llvm/dist/lib/Target/ARM/ARMTargetMachine.cpp
vendor/llvm/dist/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
vendor/llvm/dist/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
vendor/llvm/dist/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
vendor/llvm/dist/lib/Target/CellSPU/SPUCallingConv.td
vendor/llvm/dist/lib/Target/CellSPU/SPUTargetMachine.cpp
vendor/llvm/dist/lib/Target/Hexagon/CMakeLists.txt
vendor/llvm/dist/lib/Target/Hexagon/Hexagon.h
vendor/llvm/dist/lib/Target/Hexagon/HexagonAsmPrinter.cpp
vendor/llvm/dist/lib/Target/Hexagon/HexagonISelLowering.cpp
vendor/llvm/dist/lib/Target/Hexagon/HexagonInstrFormats.td
vendor/llvm/dist/lib/Target/Hexagon/HexagonInstrFormatsV4.td
vendor/llvm/dist/lib/Target/Hexagon/HexagonInstrInfo.cpp
vendor/llvm/dist/lib/Target/Hexagon/HexagonInstrInfo.h
vendor/llvm/dist/lib/Target/Hexagon/HexagonInstrInfo.td
vendor/llvm/dist/lib/Target/Hexagon/HexagonInstrInfoV3.td
vendor/llvm/dist/lib/Target/Hexagon/HexagonInstrInfoV4.td
vendor/llvm/dist/lib/Target/Hexagon/HexagonMCInstLower.cpp
vendor/llvm/dist/lib/Target/Hexagon/HexagonSchedule.td
vendor/llvm/dist/lib/Target/Hexagon/HexagonScheduleV4.td
vendor/llvm/dist/lib/Target/Hexagon/HexagonTargetMachine.cpp
vendor/llvm/dist/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.cpp
vendor/llvm/dist/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.h
vendor/llvm/dist/lib/Target/Hexagon/MCTargetDesc/CMakeLists.txt
vendor/llvm/dist/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
vendor/llvm/dist/lib/Target/MBlaze/MBlazeCallingConv.td
vendor/llvm/dist/lib/Target/MBlaze/MBlazeTargetMachine.cpp
vendor/llvm/dist/lib/Target/MSP430/MSP430TargetMachine.cpp
vendor/llvm/dist/lib/Target/Mips/CMakeLists.txt
vendor/llvm/dist/lib/Target/Mips/LLVMBuild.txt
vendor/llvm/dist/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
vendor/llvm/dist/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
vendor/llvm/dist/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
vendor/llvm/dist/lib/Target/Mips/Makefile
vendor/llvm/dist/lib/Target/Mips/Mips64InstrInfo.td
vendor/llvm/dist/lib/Target/Mips/MipsCondMov.td
vendor/llvm/dist/lib/Target/Mips/MipsISelLowering.cpp
vendor/llvm/dist/lib/Target/Mips/MipsInstrFPU.td
vendor/llvm/dist/lib/Target/Mips/MipsInstrFormats.td
vendor/llvm/dist/lib/Target/Mips/MipsInstrInfo.td
vendor/llvm/dist/lib/Target/Mips/MipsTargetMachine.cpp
vendor/llvm/dist/lib/Target/PTX/PTXTargetMachine.cpp
vendor/llvm/dist/lib/Target/PowerPC/PPCCallingConv.td
vendor/llvm/dist/lib/Target/PowerPC/PPCTargetMachine.cpp
vendor/llvm/dist/lib/Target/Sparc/SparcTargetMachine.cpp
vendor/llvm/dist/lib/Target/TargetLibraryInfo.cpp
vendor/llvm/dist/lib/Target/X86/Utils/X86ShuffleDecode.cpp
vendor/llvm/dist/lib/Target/X86/X86ISelLowering.cpp
vendor/llvm/dist/lib/Target/X86/X86ISelLowering.h
vendor/llvm/dist/lib/Target/X86/X86InstrFragmentsSIMD.td
vendor/llvm/dist/lib/Target/X86/X86InstrInfo.cpp
vendor/llvm/dist/lib/Target/X86/X86InstrSSE.td
vendor/llvm/dist/lib/Target/X86/X86Subtarget.cpp
vendor/llvm/dist/lib/Target/X86/X86TargetMachine.cpp
vendor/llvm/dist/lib/Target/XCore/XCoreTargetMachine.cpp
vendor/llvm/dist/lib/Transforms/IPO/Internalize.cpp
vendor/llvm/dist/lib/Transforms/IPO/PassManagerBuilder.cpp
vendor/llvm/dist/lib/Transforms/Scalar/LoopStrengthReduce.cpp
vendor/llvm/dist/lib/Transforms/Scalar/LoopUnswitch.cpp
vendor/llvm/dist/lib/Transforms/Scalar/ObjCARC.cpp
vendor/llvm/dist/lib/Transforms/Scalar/Reassociate.cpp
vendor/llvm/dist/lib/Transforms/Scalar/SimplifyLibCalls.cpp
vendor/llvm/dist/lib/Transforms/Utils/BreakCriticalEdges.cpp
vendor/llvm/dist/lib/Transforms/Vectorize/BBVectorize.cpp
vendor/llvm/dist/lib/VMCore/AutoUpgrade.cpp
vendor/llvm/dist/lib/VMCore/Instructions.cpp
vendor/llvm/dist/lib/VMCore/LLVMContext.cpp
vendor/llvm/dist/lib/VMCore/Module.cpp
vendor/llvm/dist/lib/VMCore/Verifier.cpp
vendor/llvm/dist/test/Analysis/ScalarEvolution/nsw-offset.ll
vendor/llvm/dist/test/Analysis/ScalarEvolution/nsw.ll
vendor/llvm/dist/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll
vendor/llvm/dist/test/CodeGen/ARM/fusedMAC.ll
vendor/llvm/dist/test/CodeGen/ARM/ldr_post.ll
vendor/llvm/dist/test/CodeGen/ARM/ldr_pre.ll
vendor/llvm/dist/test/CodeGen/ARM/tail-opts.ll
vendor/llvm/dist/test/CodeGen/ARM/vector-extend-narrow.ll
vendor/llvm/dist/test/CodeGen/ARM/widen-vmovs.ll
vendor/llvm/dist/test/CodeGen/CellSPU/2009-01-01-BrCond.ll
vendor/llvm/dist/test/CodeGen/Mips/analyzebranch.ll
vendor/llvm/dist/test/CodeGen/Mips/eh.ll
vendor/llvm/dist/test/CodeGen/Mips/fpbr.ll
vendor/llvm/dist/test/CodeGen/Thumb2/thumb2-branch.ll
vendor/llvm/dist/test/CodeGen/Thumb2/thumb2-ifcvt2.ll
vendor/llvm/dist/test/CodeGen/Thumb2/thumb2-jtb.ll
vendor/llvm/dist/test/CodeGen/X86/2006-10-19-SwitchUnnecessaryBranching.ll
vendor/llvm/dist/test/CodeGen/X86/2008-05-01-InvalidOrdCompare.ll
vendor/llvm/dist/test/CodeGen/X86/2010-08-04-MaskedSignedCompare.ll
vendor/llvm/dist/test/CodeGen/X86/2010-11-18-SelectOfExtload.ll
vendor/llvm/dist/test/CodeGen/X86/2011-09-14-valcoalesce.ll
vendor/llvm/dist/test/CodeGen/X86/atom-sched.ll
vendor/llvm/dist/test/CodeGen/X86/atomic_op.ll
vendor/llvm/dist/test/CodeGen/X86/avx2-intrinsics-x86.ll
vendor/llvm/dist/test/CodeGen/X86/block-placement.ll
vendor/llvm/dist/test/CodeGen/X86/br-fold.ll
vendor/llvm/dist/test/CodeGen/X86/call-push.ll
vendor/llvm/dist/test/CodeGen/X86/licm-dominance.ll
vendor/llvm/dist/test/CodeGen/X86/loop-blocks.ll
vendor/llvm/dist/test/CodeGen/X86/machine-cp.ll
vendor/llvm/dist/test/CodeGen/X86/postra-licm.ll
vendor/llvm/dist/test/CodeGen/X86/pr2659.ll
vendor/llvm/dist/test/CodeGen/X86/select.ll
vendor/llvm/dist/test/CodeGen/X86/sibcall.ll
vendor/llvm/dist/test/CodeGen/X86/sink-hoist.ll
vendor/llvm/dist/test/CodeGen/X86/smul-with-overflow.ll
vendor/llvm/dist/test/CodeGen/X86/sse41-blend.ll
vendor/llvm/dist/test/CodeGen/X86/sub-with-overflow.ll
vendor/llvm/dist/test/CodeGen/X86/switch-bt.ll
vendor/llvm/dist/test/CodeGen/X86/tail-opts.ll
vendor/llvm/dist/test/CodeGen/X86/uint64-to-float.ll
vendor/llvm/dist/test/CodeGen/X86/vec_shuffle-20.ll
vendor/llvm/dist/test/CodeGen/X86/xor-icmp.ll
vendor/llvm/dist/test/CodeGen/XCore/ashr.ll
vendor/llvm/dist/test/MC/ARM/neon-add-encoding.s
vendor/llvm/dist/test/MC/ARM/neon-shift-encoding.s
vendor/llvm/dist/test/MC/ARM/neon-sub-encoding.s
vendor/llvm/dist/test/MC/AsmParser/macro-args.s
vendor/llvm/dist/test/MC/Disassembler/ARM/arm-tests.txt
vendor/llvm/dist/test/MC/Disassembler/ARM/neon.txt
vendor/llvm/dist/test/MC/Disassembler/ARM/neont2.txt
vendor/llvm/dist/test/MC/Disassembler/X86/intel-syntax.txt
vendor/llvm/dist/test/MC/Mips/elf-bigendian.ll
vendor/llvm/dist/test/Transforms/GlobalOpt/constantfold-initializers.ll
vendor/llvm/dist/test/Transforms/InstCombine/apint-shift.ll
vendor/llvm/dist/test/Transforms/LoopStrengthReduce/X86/2012-01-13-phielim.ll
vendor/llvm/dist/test/Transforms/SimplifyLibCalls/floor.ll
vendor/llvm/dist/test/lit.cfg
vendor/llvm/dist/tools/llc/llc.cpp
vendor/llvm/dist/tools/lli/lli.cpp
vendor/llvm/dist/tools/llvm-mc/Disassembler.cpp
vendor/llvm/dist/tools/llvm-mc/Disassembler.h
vendor/llvm/dist/tools/llvm-mc/llvm-mc.cpp
vendor/llvm/dist/tools/llvm-shlib/Makefile
vendor/llvm/dist/tools/llvm-stress/llvm-stress.cpp
vendor/llvm/dist/tools/lto/LTOCodeGenerator.cpp
vendor/llvm/dist/tools/lto/LTOCodeGenerator.h
vendor/llvm/dist/tools/lto/lto.cpp
vendor/llvm/dist/tools/lto/lto.exports
vendor/llvm/dist/tools/opt/opt.cpp
vendor/llvm/dist/unittests/CMakeLists.txt
vendor/llvm/dist/unittests/VMCore/InstructionsTest.cpp
vendor/llvm/dist/utils/Makefile
vendor/llvm/dist/utils/TableGen/AsmMatcherEmitter.cpp
vendor/llvm/dist/utils/TableGen/AsmWriterEmitter.cpp
vendor/llvm/dist/utils/TableGen/CodeGenDAGPatterns.cpp
vendor/llvm/dist/utils/TableGen/CodeGenRegisters.cpp
vendor/llvm/dist/utils/TableGen/EDEmitter.cpp
vendor/llvm/dist/utils/TableGen/RegisterInfoEmitter.cpp
vendor/llvm/dist/utils/buildit/build_llvm
vendor/llvm/dist/utils/release/findRegressions-nightly.py
vendor/llvm/dist/utils/release/findRegressions-simple.py
vendor/llvm/dist/utils/release/tag.sh
vendor/llvm/dist/utils/release/test-release.sh
Modified: vendor/llvm/dist/CMakeLists.txt
==============================================================================
--- vendor/llvm/dist/CMakeLists.txt Thu May 3 16:49:27 2012 (r234970)
+++ vendor/llvm/dist/CMakeLists.txt Thu May 3 16:50:55 2012 (r234971)
@@ -213,15 +213,6 @@ if( WIN32 AND NOT CYGWIN )
set(LLVM_LIT_TOOLS_DIR "" CACHE PATH "Path to GnuWin32 tools")
endif()
-# On Win32 using MS tools, provide an option to set the number of parallel jobs
-# to use.
-if( MSVC_IDE AND ( MSVC90 OR MSVC10 ) )
- # Only Visual Studio 2008 and 2010 officially supports /MP. Visual Studio
- # 2005 supports it but it is experimental.
- set(LLVM_COMPILER_JOBS "0" CACHE STRING
- "Number of parallel compiler jobs. 0 means use all processors. Default is 0.")
-endif()
-
# Define options to control the inclusion and default build behavior for
# components which may not strictly be necessary (tools, runtime, examples, and
# tests).
@@ -396,7 +387,6 @@ add_subdirectory(utils/FileUpdate)
add_subdirectory(utils/count)
add_subdirectory(utils/not)
add_subdirectory(utils/llvm-lit)
-add_subdirectory(utils/json-bench)
add_subdirectory(utils/yaml-bench)
add_subdirectory(projects)
Modified: vendor/llvm/dist/CREDITS.TXT
==============================================================================
--- vendor/llvm/dist/CREDITS.TXT Thu May 3 16:49:27 2012 (r234970)
+++ vendor/llvm/dist/CREDITS.TXT Thu May 3 16:50:55 2012 (r234971)
@@ -50,9 +50,15 @@ N: Cameron Buschardt
E: buschard@uiuc.edu
D: The `mem2reg' pass - promotes values stored in memory to registers
+N: Brendon Cahoon
+E: bcahoon@codeaurora.org
+D: Loop unrolling with run-time trip counts.
+
N: Chandler Carruth
E: chandlerc@gmail.com
-D: LinkTimeOptimizer for Linux, via binutils integration, and C API
+D: Hashing algorithms and interfaces
+D: Inline cost analysis
+D: Machine block placement pass
N: Casey Carter
E: ccarter@uiuc.edu
@@ -210,6 +216,10 @@ N: Benjamin Kramer
E: benny.kra@gmail.com
D: Miscellaneous bug fixes
+N: Sundeep Kushwaha
+E: sundeepk@codeaurora.org
+D: Implemented DFA-based target independent VLIW packetizer
+
N: Christopher Lamb
E: christopher.lamb@gmail.com
D: aligned load/store support, parts of noalias and restrict support
@@ -245,6 +255,10 @@ N: Nick Lewycky
E: nicholas@mxc.ca
D: PredicateSimplifier pass
+N: Tony Linthicum, et. al.
+E: tlinth@codeaurora.org
+D: Backend for Qualcomm's Hexagon VLIW processor.
+
N: Bruno Cardoso Lopes
E: bruno.cardoso@gmail.com
W: http://www.brunocardoso.org
@@ -271,6 +285,10 @@ N: Scott Michel
E: scottm@aero.org
D: Added STI Cell SPU backend.
+N: Kai Nacke
+E: kai@redstar.de
+D: Support for implicit TLS model used with MS VC runtime
+
N: Takumi Nakamura
E: geek4civic@gmail.com
E: chapuni@hf.rim.or.jp
Modified: vendor/llvm/dist/autoconf/configure.ac
==============================================================================
--- vendor/llvm/dist/autoconf/configure.ac Thu May 3 16:49:27 2012 (r234970)
+++ vendor/llvm/dist/autoconf/configure.ac Thu May 3 16:50:55 2012 (r234971)
@@ -838,6 +838,13 @@ AC_ARG_WITH(gcc-toolchain,
AC_DEFINE_UNQUOTED(GCC_INSTALL_PREFIX,"$withval",
[Directory where gcc is installed.])
+AC_ARG_WITH(default-sysroot,
+ AS_HELP_STRING([--with-default-sysroot],
+ [Add --sysroot= to all compiler invocations.]),,
+ withval="")
+AC_DEFINE_UNQUOTED(DEFAULT_SYSROOT,"$withval",
+ [Default to all compiler invocations for --sysroot=.])
+
dnl Allow linking of LLVM with GPLv3 binutils code.
AC_ARG_WITH(binutils-include,
AS_HELP_STRING([--with-binutils-include],
Modified: vendor/llvm/dist/cmake/modules/HandleLLVMOptions.cmake
==============================================================================
--- vendor/llvm/dist/cmake/modules/HandleLLVMOptions.cmake Thu May 3 16:49:27 2012 (r234970)
+++ vendor/llvm/dist/cmake/modules/HandleLLVMOptions.cmake Thu May 3 16:50:55 2012 (r234971)
@@ -110,9 +110,9 @@ if( CMAKE_SIZEOF_VOID_P EQUAL 8 AND NOT
endif( LLVM_BUILD_32_BITS )
endif( CMAKE_SIZEOF_VOID_P EQUAL 8 AND NOT WIN32 )
-if( MSVC_IDE AND ( MSVC90 OR MSVC10 ) )
- # Only Visual Studio 2008 and 2010 officially supports /MP.
- # Visual Studio 2005 do support it but it's experimental there.
+# On Win32 using MS tools, provide an option to set the number of parallel jobs
+# to use.
+if( MSVC_IDE )
set(LLVM_COMPILER_JOBS "0" CACHE STRING
"Number of parallel compiler jobs. 0 means use all processors. Default is 0.")
if( NOT LLVM_COMPILER_JOBS STREQUAL "1" )
Modified: vendor/llvm/dist/configure
==============================================================================
--- vendor/llvm/dist/configure Thu May 3 16:49:27 2012 (r234970)
+++ vendor/llvm/dist/configure Thu May 3 16:50:55 2012 (r234971)
@@ -1442,6 +1442,7 @@ Optional Packages:
--with-c-include-dirs Colon separated list of directories clang will
search for headers
--with-gcc-toolchain Directory where gcc is installed.
+ --with-default-sysroot Add --sysroot= to all compiler invocations.
--with-binutils-include Specify path to binutils/include/ containing
plugin-api.h file for gold plugin.
--with-bug-report-url Specify the URL where bug reports should be
@@ -3802,7 +3803,7 @@ else
llvm_cv_target_os_type="Darwin" ;;
*-*-minix*)
llvm_cv_target_os_type="Minix" ;;
- *-*-freebsd*| *-*-kfreebsd-gnu)
+ *-*-freebsd* | *-*-kfreebsd-gnu)
llvm_cv_target_os_type="FreeBSD" ;;
*-*-openbsd*)
llvm_cv_target_os_type="OpenBSD" ;;
@@ -5583,6 +5584,20 @@ _ACEOF
+# Check whether --with-default-sysroot was given.
+if test "${with_default_sysroot+set}" = set; then
+ withval=$with_default_sysroot;
+else
+ withval=""
+fi
+
+
+cat >>confdefs.h <<_ACEOF
+#define DEFAULT_SYSROOT "$withval"
+_ACEOF
+
+
+
# Check whether --with-binutils-include was given.
if test "${with_binutils_include+set}" = set; then
withval=$with_binutils_include;
@@ -10386,7 +10401,7 @@ else
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <GenRegisterNames.inc file for that
architecture. For instance, by
- inspecting lib/Target/X86/X86GenRegisterNames.inc we see that the
- 32-bit register EAX is denoted by 15, and the MMX register
- MM0 is mapped to 48.
+ inspecting lib/Target/X86/X86GenRegisterInfo.inc we see that the
+ 32-bit register EAX is denoted by 43, and the MMX register
+ MM0 is mapped to 65.
Some architectures contain registers that share the same physical location. A
notable example is the X86 platform. For instance, in the X86 architecture,
@@ -1627,7 +1627,7 @@ def : Pat<(i32 imm:$imm),
bits. These physical registers are marked as aliased in LLVM. Given a
particular architecture, you can check which registers are aliased by
inspecting its RegisterInfo.td file. Moreover, the method
- TargetRegisterInfo::getAliasSet(p_reg) returns an array containing
+ MCRegisterInfo::getAliasSet(p_reg) returns an array containing
all the physical registers aliased to the register p_reg.
Physical registers, in LLVM, are grouped in Register Classes.
@@ -3182,7 +3182,7 @@ MOVSX32rm16 -> movsx, 32-bit register
Chris Lattner
The LLVM Compiler Infrastructure
- Last modified: $Date: 2012-03-27 13:25:16 +0200 (Tue, 27 Mar 2012) $
+ Last modified: $Date: 2012-04-15 22:22:36 +0200 (Sun, 15 Apr 2012) $