From owner-svn-src-all@freebsd.org Wed Dec 4 18:38:50 2019 Return-Path: Delivered-To: svn-src-all@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id EBD921AB61A; Wed, 4 Dec 2019 18:38:50 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) server-signature RSA-PSS (4096 bits) client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 47SngG5ZHBz4DBt; Wed, 4 Dec 2019 18:38:50 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id A273D4724; Wed, 4 Dec 2019 18:38:50 +0000 (UTC) (envelope-from dim@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id xB4IcoX4011953; Wed, 4 Dec 2019 18:38:50 GMT (envelope-from dim@FreeBSD.org) Received: (from dim@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id xB4IcoEN011952; Wed, 4 Dec 2019 18:38:50 GMT (envelope-from dim@FreeBSD.org) Message-Id: <201912041838.xB4IcoEN011952@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: dim set sender to dim@FreeBSD.org using -f From: Dimitry Andric Date: Wed, 4 Dec 2019 18:38:50 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r355397 - head/contrib/llvm/lib/Target/PowerPC X-SVN-Group: head X-SVN-Commit-Author: dim X-SVN-Commit-Paths: head/contrib/llvm/lib/Target/PowerPC X-SVN-Commit-Revision: 355397 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Dec 2019 18:38:51 -0000 Author: dim Date: Wed Dec 4 18:38:50 2019 New Revision: 355397 URL: https://svnweb.freebsd.org/changeset/base/355397 Log: Merge commit 241cbf201 from llvm git (by Nemanja Ivanovic): [PowerPC] Fix crash in peephole optimization When converting reg+reg shifts to reg+imm rotates, we neglect to consider the CodeGenOnly versions of the 32-bit shift mnemonics. This means we produce a rotate with missing operands which causes a crash. Committing this fix without review since it is non-controversial that the list of mnemonics to consider should include the 64-bit aliases for the exact mnemonics. Fixes PR44183. This should fix "Assertion failed: (idx < size()), function operator[], file /usr/src/contrib/llvm/include/llvm/ADT/SmallVector.h, line 153" when building the graphics/mesa-dri port for the PowerPC64 ELFv2 ABI. Reported by: Alfredo Dal'Ava Júnior MFC after: 1 month X-MFC-With: r353358 Modified: head/contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp Modified: head/contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp ============================================================================== --- head/contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp Wed Dec 4 18:21:29 2019 (r355396) +++ head/contrib/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp Wed Dec 4 18:38:50 2019 (r355397) @@ -3529,8 +3529,10 @@ bool PPCInstrInfo::transformToImmFormFedByLI(MachineIn ForwardKilledOperandReg = MI.getOperand(ConstantOpNo).getReg(); unsigned Opc = MI.getOpcode(); - bool SpecialShift32 = - Opc == PPC::SLW || Opc == PPC::SLWo || Opc == PPC::SRW || Opc == PPC::SRWo; + bool SpecialShift32 = Opc == PPC::SLW || Opc == PPC::SLWo || + Opc == PPC::SRW || Opc == PPC::SRWo || + Opc == PPC::SLW8 || Opc == PPC::SLW8o || + Opc == PPC::SRW8 || Opc == PPC::SRW8o; bool SpecialShift64 = Opc == PPC::SLD || Opc == PPC::SLDo || Opc == PPC::SRD || Opc == PPC::SRDo; bool SetCR = Opc == PPC::SLWo || Opc == PPC::SRWo ||