From owner-svn-src-all@FreeBSD.ORG Fri Mar 2 21:45:54 2012 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 48FC51065670; Fri, 2 Mar 2012 21:45:54 +0000 (UTC) (envelope-from marius@alchemy.franken.de) Received: from alchemy.franken.de (alchemy.franken.de [194.94.249.214]) by mx1.freebsd.org (Postfix) with ESMTP id CF4CD8FC12; Fri, 2 Mar 2012 21:45:53 +0000 (UTC) Received: from alchemy.franken.de (localhost [127.0.0.1]) by alchemy.franken.de (8.14.4/8.14.4/ALCHEMY.FRANKEN.DE) with ESMTP id q22LjquI073502; Fri, 2 Mar 2012 22:45:52 +0100 (CET) (envelope-from marius@alchemy.franken.de) Received: (from marius@localhost) by alchemy.franken.de (8.14.4/8.14.4/Submit) id q22LjqCv073501; Fri, 2 Mar 2012 22:45:52 +0100 (CET) (envelope-from marius) Date: Fri, 2 Mar 2012 22:45:52 +0100 From: Marius Strobl To: John Baldwin Message-ID: <20120302214551.GB1635@alchemy.franken.de> References: <201203022038.q22Kc5vd046376@svn.freebsd.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <201203022038.q22Kc5vd046376@svn.freebsd.org> User-Agent: Mutt/1.4.2.3i Cc: svn-src-head@freebsd.org, svn-src-all@freebsd.org, src-committers@freebsd.org Subject: Re: svn commit: r232403 - in head/sys: dev/acpica dev/cardbus dev/pci powerpc/ofw sparc64/pci X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 02 Mar 2012 21:45:54 -0000 On Fri, Mar 02, 2012 at 08:38:05PM +0000, John Baldwin wrote: > Author: jhb > Date: Fri Mar 2 20:38:04 2012 > New Revision: 232403 > URL: http://svn.freebsd.org/changeset/base/232403 > > Log: > - Add a bus_dma tag to each PCI bus that is a child of a Host-PCI bridge. > The tag enforces a single restriction that all DMA transactions must not > cross a 4GB boundary. Note that while this restriction technically only > applies to PCI-express, this change applies it to all PCI devices as it > is simpler to implement that way and errs on the side of caution. Hrm, wouldn't it have been more appropriate to implement this in the Host-PCI bridges instead? Probably for anything but x86 this would allow to easily distinguish at least between PCI and PCI-Express capable bus hierarchies and would move the PAE workaround to the MD bits to where it belongs. Marius