Date: Tue, 21 Nov 2000 20:05:41 -0800 From: Arun Sharma <arun@sharmas.dhs.org> To: Daniel Eischen <eischen@vigrid.com> Cc: arch@FreeBSD.ORG Subject: Re: Thread-specific data and KSEs Message-ID: <20001121200541.A21911@sharmas.dhs.org> In-Reply-To: <Pine.SUN.3.91.1001121222649.28739A-100000@pcnet1.pcnet.com>; from eischen@vigrid.com on Tue, Nov 21, 2000 at 10:33:50PM -0500 References: <20001121192331.E18037@fw.wintelcom.net> <Pine.SUN.3.91.1001121222649.28739A-100000@pcnet1.pcnet.com>
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On Tue, Nov 21, 2000 at 10:33:50PM -0500, Daniel Eischen wrote: > On Tue, 21 Nov 2000, Alfred Perlstein wrote: > > * Daniel Eischen <eischen@vigrid.com> [001121 19:15] wrote: > > > > > > > > Don't more segment registers cause more overhead for context switches? > > > > > > It's just one more register that has to be saved. I don't > > > think it's going to matter much. > > > > No extra TLB faults/invalidations? Aren't segment registers > > somewhat expensive to load? > > Not according to swtch.s, it's just a movl instruction. I don't > need to use the segment register to address anything. I just > need to load it with a value (an index into a global array > of per-KSE structures). Loading a segment register on x86 results in privilege level checking. It may even generate a general protection fault. Section 4.6 of vol 3 (system programming guide) from Intel has more details. -Arun To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-arch" in the body of the message
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