From owner-svn-src-all@freebsd.org Thu Oct 6 12:01:12 2016 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 09F14AF52E0; Thu, 6 Oct 2016 12:01:12 +0000 (UTC) (envelope-from mmel@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id CE68F961; Thu, 6 Oct 2016 12:01:11 +0000 (UTC) (envelope-from mmel@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u96C1Blh060569; Thu, 6 Oct 2016 12:01:11 GMT (envelope-from mmel@FreeBSD.org) Received: (from mmel@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u96C1ARn060568; Thu, 6 Oct 2016 12:01:10 GMT (envelope-from mmel@FreeBSD.org) Message-Id: <201610061201.u96C1ARn060568@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: mmel set sender to mmel@FreeBSD.org using -f From: Michal Meloun Date: Thu, 6 Oct 2016 12:01:10 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r306755 - in head/sys/arm: arm include X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 06 Oct 2016 12:01:12 -0000 Author: mmel Date: Thu Oct 6 12:01:10 2016 New Revision: 306755 URL: https://svnweb.freebsd.org/changeset/base/306755 Log: ARM: Add identifiers for ARM Cortex v8 and Marvell Sheeva v7 cores. Not a functional change. MFC after: 3 days Modified: head/sys/arm/arm/cpuinfo.c head/sys/arm/include/cpuinfo.h Modified: head/sys/arm/arm/cpuinfo.c ============================================================================== --- head/sys/arm/arm/cpuinfo.c Thu Oct 6 11:54:42 2016 (r306754) +++ head/sys/arm/arm/cpuinfo.c Thu Oct 6 12:01:10 2016 (r306755) @@ -165,7 +165,11 @@ cpuinfo_get_actlr_modifier(uint32_t *act if (cpuinfo.implementer == CPU_IMPLEMENTER_ARM) { switch (cpuinfo.part_number) { - + case CPU_ARCH_CORTEX_A72: + case CPU_ARCH_CORTEX_A57: + case CPU_ARCH_CORTEX_A53: + /* Nothing to do for AArch32 */ + break; case CPU_ARCH_CORTEX_A17: case CPU_ARCH_CORTEX_A12: /* A12 is merged to A17 */ /* Modified: head/sys/arm/include/cpuinfo.h ============================================================================== --- head/sys/arm/include/cpuinfo.h Thu Oct 6 11:54:42 2016 (r306754) +++ head/sys/arm/include/cpuinfo.h Thu Oct 6 12:01:10 2016 (r306755) @@ -45,10 +45,18 @@ #define CPU_ARCH_CORTEX_A12 0xC0D #define CPU_ARCH_CORTEX_A15 0xC0F #define CPU_ARCH_CORTEX_A17 0xC11 +#define CPU_ARCH_CORTEX_A53 0xD03 +#define CPU_ARCH_CORTEX_A57 0xD07 +#define CPU_ARCH_CORTEX_A72 0xD08 + /* QCOM */ #define CPU_ARCH_KRAIT_300 0x06F +/* MRVL */ +#define CPU_ARCH_SHEEVA_851 0x581 /* PJ4/PJ4B */ +#define CPU_ARCH_SHEEVA_584 0x584 /* PJ4B-MP/PJ4C */ + struct cpuinfo { /* raw id registers */ uint32_t midr;