Date: Sat, 28 Jun 2003 00:44:21 -0700 From: Terry Lambert <tlambert2@mindspring.com> To: Andrew Gallatin <gallatin@cs.duke.edu> Cc: freebsd-arch@freebsd.org Subject: Re: API change for bus_dma Message-ID: <3EFD4755.49BAF150@mindspring.com> References: <3EF3C12F.9060303@btc.adaptec.com> <16124.39930.142492.356163@grasshopper.cs.duke.edu> <3EFC9F2D.6020908@btc.adaptec.com> <16124.43999.333761.397624@grasshopper.cs.duke.edu> <16124.45051.919899.414795@grasshopper.cs.duke.edu>
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Andrew Gallatin wrote: > Most sparc's have 2 different sorts of DMA modes. One is cache > coherent (aka DDI_DMA_CONSISTENT) -- this is what we all know and love > from PC, alphas, macs, etc. "contiguous" > The other mode (DDI_DMA_STREAMING) allows non cache coherent DMA. > This requires you to call ddi_dma_sync() between your last touch of > the data and you starting a DMA read from a device. And vice-versa > for a DMA write. "scatter/gather" > The reason people use DDI_DMA_STREAMING is because coherent DMA > bandwith tends to be abysmal on most sparcs. I'm not surprised; in order to present a contiguous physical RAM buffer to the device DMA engine, you have two choices: 1) Get lucky 2) Copy the data before triggering the DMA The data copy is what kills you. -- Terry
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