Date: Wed, 29 Mar 2017 04:26:41 +0000 From: bugzilla-noreply@freebsd.org To: freebsd-bugs@FreeBSD.org Subject: [Bug 218203] Implement AVX2 accelerated Fletcher algorithms Message-ID: <bug-218203-8@https.bugs.freebsd.org/bugzilla/>
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https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=3D218203 Bug ID: 218203 Summary: Implement AVX2 accelerated Fletcher algorithms Product: Base System Version: CURRENT Hardware: amd64 OS: Any Status: New Severity: Affects Only Me Priority: --- Component: kern Assignee: freebsd-bugs@FreeBSD.org Reporter: kungfujesus06@gmail.com Intel has published a pretty straight forward implementation of Fletcher4 leveraging AVX2 instructions:=20=20 https://software.intel.com/en-us/articles/fast-computation-of-fletcher-chec= ksums I was able to use this white paper and compiler intrinsics to build a rudimentary version that's nearly twice as fast. It is feasible to swap out the existing scalar and portable implementation for this faster variant sim= ilar to the way Linux offers SIMD accelerated versions of cryptographic and hash= ing routines within their kernel.=20=20 As a matter of fact, zfsonlinux is already doing this: https://github.com/zfsonlinux/zfs/tree/482cd9ee69e88710e9241fac220501ea4e10= 1d19/module/zcommon While I understand the desire to remain close to the reference ZFS implementation with Illumos and maybe there doesn't need to be quite that m= any versions of fletcher4 (they do a superscalar version that presumably tries = to take advantage of Out-of-Order execution - hoping the microarchitecture can schedule the instructions efficiently by noticing the lack of data dependencies), it does seem silly to ignore a working implementation that is measurably faster for CPUs that support it. It has even been backported to SSSE3 instructions: https://github.com/zfsonlinux/zfs/blob/482cd9ee69e88710e9241fac220501ea4e10= 1d19/module/zcommon/zfs_fletcher_sse.c --=20 You are receiving this mail because: You are the assignee for the bug.=
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