From owner-svn-src-head@FreeBSD.ORG Sat Jun 8 20:21:18 2013 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.FreeBSD.org [8.8.178.115]) by hub.freebsd.org (Postfix) with ESMTP id 48D198AF; Sat, 8 Jun 2013 20:21:18 +0000 (UTC) (envelope-from adrian@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) by mx1.freebsd.org (Postfix) with ESMTP id 2ABB4125E; Sat, 8 Jun 2013 20:21:18 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.7/8.14.7) with ESMTP id r58KLIjC096719; Sat, 8 Jun 2013 20:21:18 GMT (envelope-from adrian@svn.freebsd.org) Received: (from adrian@localhost) by svn.freebsd.org (8.14.7/8.14.5/Submit) id r58KLHrA096717; Sat, 8 Jun 2013 20:21:17 GMT (envelope-from adrian@svn.freebsd.org) Message-Id: <201306082021.r58KLHrA096717@svn.freebsd.org> From: Adrian Chadd Date: Sat, 8 Jun 2013 20:21:17 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r251551 - head/sys/mips/conf X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 08 Jun 2013 20:21:18 -0000 Author: adrian Date: Sat Jun 8 20:21:17 2013 New Revision: 251551 URL: http://svnweb.freebsd.org/changeset/base/251551 Log: Add 8devices CARAMBOLA2 support. This is based on the AR933x (Hornet) SoC from Qualcomm Atheros. It's a much nicer board to do development on - 64MB RAM, 16MB flash. The development board breaks out the GPIO pins, ethernet, serial (via a USB<->RS232 chip), USB host and of course a small wifi antenna. Everything but the wifi works thus far. Added: head/sys/mips/conf/CARAMBOLA2 (contents, props changed) head/sys/mips/conf/CARAMBOLA2.hints (contents, props changed) Added: head/sys/mips/conf/CARAMBOLA2 ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/mips/conf/CARAMBOLA2 Sat Jun 8 20:21:17 2013 (r251551) @@ -0,0 +1,53 @@ +# +# Carambola 2 - an AR933x based SoC wifi device. +# +# http://shop.8devices.com/wifi4things/carambola2 +# +# * AR9330 SoC +# * 64MB RAM +# * 16MB flash +# * Integrated 1x1 2GHz wifi and 10/100 bridge +# +# $FreeBSD$ +# + +# Include the default AR933x parameters +include "AR933X_BASE" + +ident CARAMBOLA2 + +# Override hints with board values +hints "CARAMBOLA2.hints" + +# Board memory - 64MB +options AR71XX_REALMEM=(64*1024*1024) + +# i2c GPIO bus +#device gpioiic +#device iicbb +#device iicbus +#device iic + +# Options required for miiproxy and mdiobus +options ARGE_MDIO # Export an MDIO bus separate from arge +device miiproxy # MDIO bus <-> MII PHY rendezvous + +device etherswitch +device arswitch + +# read MSDOS formatted disks - USB +#options MSDOSFS + +# Enable the uboot environment stuff rather then the +# redboot stuff. +options AR71XX_ENV_UBOOT + +# uzip - to boot natively from flash +device geom_uncompress +options GEOM_UNCOMPRESS + +# Used for the static uboot partition map +device geom_map + +# Boot off of the rootfs, as defined in the geom_map setup. +options ROOTDEVNAME=\"ufs:map/rootfs.uncompress\" Added: head/sys/mips/conf/CARAMBOLA2.hints ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/mips/conf/CARAMBOLA2.hints Sat Jun 8 20:21:17 2013 (r251551) @@ -0,0 +1,109 @@ +# +# This file adds to the values in AR91XX_BASE.hints. +# +# $FreeBSD$ + +# mdiobus on arge1 +hint.argemdio.0.at="nexus0" +hint.argemdio.0.maddr=0x1a000000 +hint.argemdio.0.msize=0x1000 +hint.argemdio.0.order=0 + +# Embedded Atheros Switch +hint.arswitch.0.at="mdio0" + +# XXX this should really say it's an AR933x switch, as there +# are some vlan specific differences here! +hint.arswitch.0.is_7240=1 +hint.arswitch.0.numphys=4 +hint.arswitch.0.phy4cpu=1 # phy 4 is a "CPU" separate PHY +hint.arswitch.0.is_rgmii=0 +hint.arswitch.0.is_gmii=1 # arge1 <-> switch PHY is GMII + +# arge0 - MII, autoneg, phy(4) +hint.arge.0.phymask=0x10 # PHY4 +hint.arge.0.mdio=mdioproxy1 # .. off of the switch mdiobus + +# arge1 - GMII, 1000/full +hint.arge.1.phymask=0x0 # No directly mapped PHYs +hint.arge.1.media=1000 +hint.arge.1.fduplex=1 + +# The AP121 16MB flash layout: +# +# [ 0.700000] 0x000000000000-0x000000040000 : "u-boot" +# [ 0.710000] 0x000000040000-0x000000050000 : "u-boot-env" +# [ 0.710000] 0x000000050000-0x000000250000 : "kernel" +# [ 0.720000] 0x000000250000-0x000000fe0000 : "rootfs" +# [ 0.720000] mtd: partition "rootfs" set to be root filesystem +# [ 0.730000] mtd: partition "rootfs_data" created automatically, ofs=480000, len=B60000 +# [ 0.740000] 0x000000480000-0x000000fe0000 : "rootfs_data" +# [ 0.740000] 0x000000fe0000-0x000000ff0000 : "nvram" +# [ 0.750000] 0x000000ff0000-0x000001000000 : "art" +# [ 0.750000] 0x000000050000-0x000000fe0000 : "firmware" + +hint.map.0.at="flash/spi0" +hint.map.0.start=0x00000000 +hint.map.0.end=0x000040000 +hint.map.0.name="uboot" +hint.map.0.readonly=1 + +hint.map.1.at="flash/spi0" +hint.map.1.start=0x00040000 +hint.map.1.end=0x00050000 +hint.map.1.name="uboot-env" +hint.map.1.readonly=0 + +hint.map.2.at="flash/spi0" +hint.map.2.start=0x00050000 +hint.map.2.end=0x00250000 +hint.map.2.name="kernel" +hint.map.2.readonly=0 + +hint.map.3.at="flash/spi0" +hint.map.3.start=0x00250000 +hint.map.3.end=0x00fe0000 +hint.map.3.name="rootfs" +hint.map.3.readonly=0 + +hint.map.4.at="flash/spi0" +hint.map.4.start=0x00fe0000 +hint.map.4.end=0x00ff0000 +hint.map.4.name="cfg" +hint.map.4.readonly=0 + +# This is radio calibration section. It is (or should be!) unique +# for each board, to take into account thermal and electrical differences +# as well as the regulatory compliance data. +# +hint.map.5.at="flash/spi0" +hint.map.5.start=0x00ff0000 +hint.map.5.end=0x01000000 +hint.map.5.name="art" +hint.map.5.readonly=1 + +# GPIO specific configuration block + +# Don't flip on anything that isn't already enabled. +# This includes leaving the SPI CS1/CS2 pins as GPIO pins as they're +# not used here. +hint.gpio.0.function_set=0x00000000 +hint.gpio.0.function_clear=0x00000000 + +# These are the GPIO LEDs and buttons which can be software controlled. +#hint.gpio.0.pinmask=0x001c02ae +hint.gpio.0.pinmask=0x00001803 + +# gpio0 - WLAN LED +# gpio1 - USB LED +# gpio11 - Jumpstart button +# gpio12 - Reset button + +# LEDs are configured separately and driven by the LED device +hint.gpioled.0.at="gpiobus0" +hint.gpioled.0.name="wlan" +hint.gpioled.0.pins=0x0001 + +hint.gpioled.1.at="gpiobus0" +hint.gpioled.1.name="usb" +hint.gpioled.1.pins=0x0002