Date: Wed, 17 Apr 2024 20:56:02 +0000 From: bugzilla-noreply@freebsd.org To: toolchain@FreeBSD.org Subject: [Bug 278417] The _cvtsh_ss() intrinsic function generates illegal instructions Message-ID: <bug-278417-29464-yaP1bI1OTl@https.bugs.freebsd.org/bugzilla/> In-Reply-To: <bug-278417-29464@https.bugs.freebsd.org/bugzilla/> References: <bug-278417-29464@https.bugs.freebsd.org/bugzilla/>
next in thread | previous in thread | raw e-mail | index | archive | help
https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=3D278417 Mark Millard <marklmi26-fbsd@yahoo.com> changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |marklmi26-fbsd@yahoo.com --- Comment #1 from Mark Millard <marklmi26-fbsd@yahoo.com> --- For reference: static __inline float __DEFAULT_FN_ATTRS128 _cvtsh_ss (unsigned short _= _a) Converts a 16-bit half-precision float value into a 32-bit float va= lue. Quoting https://en.wikipedia.org/wiki/Half-precision_floating-point_format : Support for half precision in the x86 instruction set is specified in the F= 16C instruction set extension, first introduced in 2009 by AMD and fairly broad= ly adopted by AMD and Intel CPUs by 2012. This was further extended up the AVX-512_FP16 instruction set extension implemented in the Intel Sapphire Ra= pids processor. Quoting https://en.wikipedia.org/wiki/F16C : The F16C[1] (previously/informally known as CVT16) instruction set is an x86 instruction set architecture extension which provides support for converting between half-precision and standard IEEE single-precision floating-point formats. Is your hardware missing the F16C instruction set extension? --=20 You are receiving this mail because: You are the assignee for the bug.=
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?bug-278417-29464-yaP1bI1OTl>