Date: Thu, 6 Nov 2003 13:58:03 -0500 From: Charles Swiger <cswiger@mac.com> To: "Jack L. Stone" <jacks@sage-american.com> Cc: freebsd <freebsd-questions@freebsd.org> Subject: Re: lan bandwidth issue Message-ID: <264C8786-108B-11D8-AD24-003065ABFD92@mac.com> In-Reply-To: <3.0.5.32.20031106092614.01465da8@10.0.0.15> References: <Sea2-F26IAdigQDzBE600077a74@hotmail.com> <Sea2-F26IAdigQDzBE600077a74@hotmail.com> <3.0.5.32.20031106092614.01465da8@10.0.0.15>
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On Nov 6, 2003, at 10:26 AM, Jack L. Stone wrote: > This "price advice" then implies that if Realtek simply raised their > prices, the card would be just fine...?? No. The price advice implies that a NIC that is worth $5 is probably not as good as a NIC which is worth $50. If Realtek raised their prices, their cards would become overpriced "cheapo" NICs rather than cheap "cheapo" NICs. :-) > One should not just go by "expensive", but do some research not just > based > on that "easy" benchmark. The "cheapo" measurement is very misleading > considering some cards may just be "on sale" and are fine cards. ...or > just > because they use the rlx driver.... Speaking of which, /usr/src/sys/pci/rl.c provides some very specific technical details as to the design flaws with this chipset family: /* * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is * probably the worst PCI ethernet controller ever made, with the possible * exception of the FEAST chip made by SMC. The 8139 supports bus-master * DMA, but it has a terrible interface that nullifies any performance * gains that bus-master DMA usually offers. * * For transmission, the chip offers a series of four TX descriptor * registers. Each transmit frame must be in a contiguous buffer, aligned * on a longword (32-bit) boundary. This means we almost always have to * do mbuf copies in order to transmit a frame, except in the unlikely * case where a) the packet fits into a single mbuf, and b) the packet * is 32-bit aligned within the mbuf's data area. The presence of only * four descriptor registers means that we can never have more than four * packets queued for transmission at any one time. * * Reception is not much better. The driver has to allocate a single large * buffer area (up to 64K in size) into which the chip will DMA received * frames. Because we don't know where within this region received packets * will begin or end, we have no choice but to copy data from the buffer * area into mbufs in order to pass the packets up to the higher protocol * levels. * * It's impossible given this rotten design to really achieve decent * performance at 100Mbps, unless you happen to have a 400Mhz PII or * some equally overmuscled CPU to drive it. -- -Chuck
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