From owner-svn-src-head@FreeBSD.ORG Sun Nov 16 20:34:14 2014 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id C97D2CC7; Sun, 16 Nov 2014 20:34:14 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id B6034654; Sun, 16 Nov 2014 20:34:14 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.9/8.14.9) with ESMTP id sAGKYEJ4088654; Sun, 16 Nov 2014 20:34:14 GMT (envelope-from ian@FreeBSD.org) Received: (from ian@localhost) by svn.freebsd.org (8.14.9/8.14.9/Submit) id sAGKYEwt088653; Sun, 16 Nov 2014 20:34:14 GMT (envelope-from ian@FreeBSD.org) Message-Id: <201411162034.sAGKYEwt088653@svn.freebsd.org> X-Authentication-Warning: svn.freebsd.org: ian set sender to ian@FreeBSD.org using -f From: Ian Lepore Date: Sun, 16 Nov 2014 20:34:14 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r274596 - head/sys/arm/arm X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 16 Nov 2014 20:34:14 -0000 Author: ian Date: Sun Nov 16 20:34:14 2014 New Revision: 274596 URL: https://svnweb.freebsd.org/changeset/base/274596 Log: Indent a couple lines properly and expand a comment. No functional changes. Modified: head/sys/arm/arm/busdma_machdep-v6.c Modified: head/sys/arm/arm/busdma_machdep-v6.c ============================================================================== --- head/sys/arm/arm/busdma_machdep-v6.c Sun Nov 16 20:29:57 2014 (r274595) +++ head/sys/arm/arm/busdma_machdep-v6.c Sun Nov 16 20:34:14 2014 (r274596) @@ -1336,7 +1336,7 @@ _bus_dmamap_sync(bus_dma_tag_t dmat, bus (void *)bpage->vaddr, bpage->datacount); cpu_dcache_wb_range((vm_offset_t)bpage->vaddr, - bpage->datacount); + bpage->datacount); l2cache_wb_range((vm_offset_t)bpage->vaddr, (vm_offset_t)bpage->busaddr, bpage->datacount); @@ -1390,12 +1390,16 @@ _bus_dmamap_sync(bus_dma_tag_t dmat, bus /* * For COHERENT memory no cache maintenance is necessary, but ensure all - * writes have reached memory for the PREWRITE case. + * writes have reached memory for the PREWRITE case. No action is + * needed for a PREREAD without PREWRITE also set, because that would + * imply that the cpu had written to the COHERENT buffer and expected + * the dma device to see that change, and by definition a PREWRITE sync + * is required to make that happen. */ if (map->flags & DMAMAP_COHERENT) { if (op & BUS_DMASYNC_PREWRITE) { - dsb(); - cpu_l2cache_drain_writebuf(); + dsb(); + cpu_l2cache_drain_writebuf(); } return; }