Date: Mon, 9 Nov 2020 13:45:01 +0000 (UTC) From: Mitchell Horne <mhorne@FreeBSD.org> To: ports-committers@freebsd.org, svn-ports-all@freebsd.org, svn-ports-head@freebsd.org Subject: svn commit: r554722 - in head: . emulators/riscv-fesvr emulators/riscv-isa-sim emulators/riscv-isa-sim/files Message-ID: <202011091345.0A9Dj1ab068797@repo.freebsd.org>
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Author: mhorne (src committer) Date: Mon Nov 9 13:45:01 2020 New Revision: 554722 URL: https://svnweb.freebsd.org/changeset/ports/554722 Log: Update riscv-isa-sim to 2020-11-02 snapshot - Switch to the official upstream, github.com/riscv/riscv-isa-sim. - Remove emulators/riscv-fesvr, as it is now bundled with Spike. - Drop patches. Submitted by: lwhsu (earlier version) Reviewed by: lwhsu Approved by: lwhsu (ports, maintainer) Differential Revision: https://reviews.freebsd.org/D27144 Deleted: head/emulators/riscv-fesvr/ head/emulators/riscv-isa-sim/files/ Modified: head/MOVED head/emulators/riscv-isa-sim/Makefile head/emulators/riscv-isa-sim/distinfo head/emulators/riscv-isa-sim/pkg-descr head/emulators/riscv-isa-sim/pkg-plist Modified: head/MOVED ============================================================================== --- head/MOVED Mon Nov 9 13:43:03 2020 (r554721) +++ head/MOVED Mon Nov 9 13:45:01 2020 (r554722) @@ -15680,3 +15680,4 @@ multimedia/swfdec-gnome||2020-11-09|Depends on the exp grapihcs/swfdec||2020-11-09|Depends on the expired gstreamer 0.10 multimedia/py-openlp||2020-11-09|Depends on the expired gstreamer 0.10 multimedia/p5-GStreamer||2020-11-09|Depends on the expired gstreamer 0.10 +emulators/riscv-fesvr||2020-11-09|Now bundled with emulators/riscv-isa-sim Modified: head/emulators/riscv-isa-sim/Makefile ============================================================================== --- head/emulators/riscv-isa-sim/Makefile Mon Nov 9 13:43:03 2020 (r554721) +++ head/emulators/riscv-isa-sim/Makefile Mon Nov 9 13:45:01 2020 (r554722) @@ -2,7 +2,7 @@ PORTNAME= riscv-isa-sim DISTVERSION= git -PORTREVISION= 20181007 +PORTREVISION= 20201102 CATEGORIES= emulators MAINTAINER= lwhsu@FreeBSD.org @@ -12,33 +12,27 @@ LICENSE= BSD3CLAUSE ONLY_FOR_ARCHS= amd64 -LIB_DEPENDS= libfesvr.so:emulators/riscv-fesvr - USES= compiler:c++11-lang gmake shebangfix -GH_ACCOUNT= freebsd-riscv -GH_TAGNAME= aae60e0 +GH_ACCOUNT= riscv +GH_TAGNAME= 641d7d0 HAS_CONFIGURE= yes SHEBANG_FILES= scripts/vcs-version.sh + USE_GITHUB= yes USE_LDCONFIG= yes -LDFLAGS+= -L${LOCALBASE}/lib -CFLAGS+= -I${LOCALBASE}/include \ - -DRISCV_ENABLE_DIRTY=1 +CFLAGS+= -DRISCV_ENABLE_DIRTY=1 -STRIP_FILES= bin/spike \ +STRIP_FILES= bin/elf2hex \ + bin/spike \ bin/spike-dasm \ + bin/spike-log-parser \ bin/termios-xspike \ bin/xspike \ - lib/libdummy_rocc.so \ - lib/libriscv.so \ - lib/libsoftfloat.so \ - lib/libspike_main.so - -post-extract: - @${MV} ${WRKSRC}/riscv/insn_template.h ${WRKSRC}/riscv/insn_template.hpp + lib/libcustomext.so \ + lib/libsoftfloat.so post-patch: ${REINPLACE_CMD} -e \ Modified: head/emulators/riscv-isa-sim/distinfo ============================================================================== --- head/emulators/riscv-isa-sim/distinfo Mon Nov 9 13:43:03 2020 (r554721) +++ head/emulators/riscv-isa-sim/distinfo Mon Nov 9 13:45:01 2020 (r554722) @@ -1,3 +1,3 @@ -TIMESTAMP = 1538736497 -SHA256 (freebsd-riscv-riscv-isa-sim-git-aae60e0_GH0.tar.gz) = 423005144e71b272fad7f13b57af7de561a178af096a71d304e0a3c590520195 -SIZE (freebsd-riscv-riscv-isa-sim-git-aae60e0_GH0.tar.gz) = 232817 +TIMESTAMP = 1604881926 +SHA256 (riscv-riscv-isa-sim-git-641d7d0_GH0.tar.gz) = 810c0567ba31459a37bd84498071c68b1a85b8dc7f891df800b02201544e5149 +SIZE (riscv-riscv-isa-sim-git-641d7d0_GH0.tar.gz) = 385330 Modified: head/emulators/riscv-isa-sim/pkg-descr ============================================================================== --- head/emulators/riscv-isa-sim/pkg-descr Mon Nov 9 13:43:03 2020 (r554721) +++ head/emulators/riscv-isa-sim/pkg-descr Mon Nov 9 13:45:01 2020 (r554722) @@ -3,4 +3,4 @@ Spike, a RISC-V ISA Simulator The RISC-V ISA Simulator implements a functional model of one or more RISC-V processors. -WWW: https://github.com/freebsd-riscv/riscv-isa-sim +WWW: https://github.com/riscv/riscv-isa-sim Modified: head/emulators/riscv-isa-sim/pkg-plist ============================================================================== --- head/emulators/riscv-isa-sim/pkg-plist Mon Nov 9 13:43:03 2020 (r554721) +++ head/emulators/riscv-isa-sim/pkg-plist Mon Nov 9 13:45:01 2020 (r554722) @@ -1,44 +1,27 @@ +bin/elf2hex bin/spike bin/spike-dasm +bin/spike-log-parser bin/termios-xspike bin/xspike -include/spike/cachesim.h -include/spike/common.h -include/spike/config.h -include/spike/debug_module.h -include/spike/debug_rom_defines.h -include/spike/decode.h -include/spike/devices.h -include/spike/disasm.h -include/spike/dts.h -include/spike/encoding.h -include/spike/extension.h -include/spike/icache.h -include/spike/insn_list.h -include/spike/insn_template.hpp -include/spike/internals.h -include/spike/jtag_dtm.h -include/spike/memtracer.h -include/spike/mmu.h -include/spike/mulhi.h -include/spike/platform.h -include/spike/primitiveTypes.h -include/spike/primitives.h -include/spike/processor.h -include/spike/remote_bitbang.h -include/spike/rocc.h -include/spike/sim.h -include/spike/simif.h -include/spike/softfloat.h -include/spike/softfloat_types.h -include/spike/specialize.h -include/spike/tracer.h -include/spike/trap.h -lib/libdummy_rocc.so -lib/libriscv.so +include/fesvr/context.h +include/fesvr/device.h +include/fesvr/dtm.h +include/fesvr/elf.h +include/fesvr/elfloader.h +include/fesvr/htif.h +include/fesvr/htif_hexwriter.h +include/fesvr/htif_pthread.h +include/fesvr/memif.h +include/fesvr/option_parser.h +include/fesvr/rfb.h +include/fesvr/syscall.h +include/fesvr/term.h +include/fesvr/tsi.h +include/riscv/mmio_plugin.h +lib/libcustomext.so +lib/libdisasm.a +lib/libfesvr.a lib/libsoftfloat.so -lib/libspike_main.so -libdata/pkgconfig/riscv-dummy_rocc.pc -libdata/pkgconfig/riscv-riscv.pc -libdata/pkgconfig/riscv-softfloat.pc -libdata/pkgconfig/riscv-spike_main.pc +libdata/pkgconfig/riscv-disasm.pc +libdata/pkgconfig/riscv-fesvr.pc
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