From owner-svn-src-head@freebsd.org Sun Nov 29 11:28:05 2015 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id D538AA3C889; Sun, 29 Nov 2015 11:28:05 +0000 (UTC) (envelope-from mmel@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 8530610B0; Sun, 29 Nov 2015 11:28:05 +0000 (UTC) (envelope-from mmel@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id tATBS4q0058157; Sun, 29 Nov 2015 11:28:04 GMT (envelope-from mmel@FreeBSD.org) Received: (from mmel@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id tATBS48l058154; Sun, 29 Nov 2015 11:28:04 GMT (envelope-from mmel@FreeBSD.org) Message-Id: <201511291128.tATBS48l058154@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: mmel set sender to mmel@FreeBSD.org using -f From: Michal Meloun Date: Sun, 29 Nov 2015 11:28:04 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r291444 - head/sys/dev/ahci X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 29 Nov 2015 11:28:05 -0000 Author: mmel Date: Sun Nov 29 11:28:04 2015 New Revision: 291444 URL: https://svnweb.freebsd.org/changeset/base/291444 Log: AHCI: Fix AHCI driver for ARM. On ARM, we must ensure proper interdevice write ordering. The AHCI interrupt status register must be updated in HW before registers in interrupt controller. Unfortunately, only way how we can do it is readback. Discussed with: mav Approved by: kib (mentor) Differential Revision: https://reviews.freebsd.org/D4240 Modified: head/sys/dev/ahci/ahci.c head/sys/dev/ahci/ahci.h Modified: head/sys/dev/ahci/ahci.c ============================================================================== --- head/sys/dev/ahci/ahci.c Sun Nov 29 07:20:30 2015 (r291443) +++ head/sys/dev/ahci/ahci.c Sun Nov 29 11:28:04 2015 (r291444) @@ -483,6 +483,7 @@ ahci_intr(void *data) /* AHCI declares level triggered IS. */ if (!(ctlr->quirks & AHCI_Q_EDGEIS)) ATA_OUTL(ctlr->r_mem, AHCI_IS, is); + ATA_RBL(ctlr->r_mem, AHCI_IS); } /* @@ -501,6 +502,7 @@ ahci_intr_one(void *data) ctlr->interrupt[unit].function(arg); /* AHCI declares level triggered IS. */ ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); + ATA_RBL(ctlr->r_mem, AHCI_IS); } static void @@ -516,6 +518,7 @@ ahci_intr_one_edge(void *data) ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit); if ((arg = ctlr->interrupt[unit].argument)) ctlr->interrupt[unit].function(arg); + ATA_RBL(ctlr->r_mem, AHCI_IS); } struct resource * Modified: head/sys/dev/ahci/ahci.h ============================================================================== --- head/sys/dev/ahci/ahci.h Sun Nov 29 07:20:30 2015 (r291443) +++ head/sys/dev/ahci/ahci.h Sun Nov 29 11:28:04 2015 (r291444) @@ -562,6 +562,20 @@ enum ahci_err_type { #define ATA_OUTSL_STRM(res, offset, addr, count) \ bus_write_multi_stream_4((res), (offset), (addr), (count)) +/* + * On some platforms, we must ensure proper interdevice write ordering. + * The AHCI interrupt status register must be updated in HW before + * registers in interrupt controller. + * Unfortunately, only way how we can do it is readback. + * + * Currently, only ARM is known to have this issue. + */ +#if defined(__arm__) +#define ATA_RBL(res, offset) \ + bus_read_4((res), (offset)) +#else +#define ATA_RBL(res, offset) +#endif #define AHCI_Q_NOFORCE 0x00000001 #define AHCI_Q_NOPMP 0x00000002