From owner-freebsd-embedded@FreeBSD.ORG Wed Nov 30 20:16:53 2011 Return-Path: Delivered-To: freebsd-embedded@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 462EC1065670 for ; Wed, 30 Nov 2011 20:16:53 +0000 (UTC) (envelope-from stb@lassitu.de) Received: from gilb.zs64.net (gilb.zs64.net [IPv6:2001:470:1f0b:105e::1ea]) by mx1.freebsd.org (Postfix) with ESMTP id 0A0FC8FC13 for ; Wed, 30 Nov 2011 20:16:53 +0000 (UTC) Received: by gilb.zs64.net (Postfix, from stb@lassitu.de) id DCB1D113AFB; Wed, 30 Nov 2011 21:16:51 +0100 (CET) Mime-Version: 1.0 (Apple Message framework v1251.1) Content-Type: text/plain; charset=windows-1252 From: Stefan Bethke In-Reply-To: <2B8826C7-00C7-4117-B424-4A86F1346DFF@bsdimp.com> Date: Wed, 30 Nov 2011 21:16:51 +0100 Content-Transfer-Encoding: quoted-printable Message-Id: <2ED0CD2A-7D7B-438D-AE00-B9DF947D01B3@lassitu.de> References: <68ABED76-CB1F-405A-8036-EC254F7511FA@lassitu.de> <3B3DB17D-BF87-40EE-B1C1-445F178E8844@lassitu.de> <86030CEE-6839-4B96-ACDC-2BA9AC1E4AE4@lassitu.de> <2D625CC9-A0E3-47AA-A504-CE8FB2F90245@lassitu.de> <203BF1C8-D528-40C9-8611-9C7AC7E43BAB@lassitu.de> <3C0E9CA3-E130-4E9A-ABCC-1782E28999D1@lassitu.de> <2B8826C7-00C7-4117-B424-4A86F1346DFF@bsdimp.com> To: Warner Losh X-Mailer: Apple Mail (2.1251.1) Cc: freebsd-embedded@freebsd.org Subject: Re: TL-WR1043: switch X-BeenThere: freebsd-embedded@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Dedicated and Embedded Systems List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 30 Nov 2011 20:16:53 -0000 Am 30.11.2011 um 20:58 schrieb Warner Losh: > On Nov 30, 2011, at 12:43 PM, Stefan Bethke wrote: >=20 >> The I2C framework makes a faulty assumption that the read/not-write = bit of the first byte (the address) indicates whether reads or writes = are to follow. While many simple I2C devices usually will follow this = rule, it's not prescribed by the protocol (AFAICT), and is incompatible = with the way the RTL8366 familiy uses the bus: after sending the = address+read/not-write byte, two register address bytes are sent, then = the 16-bit register value is sent or received. While the register write = access can be performed as a 4-byte write, the read access requires the = read bit to be set, but the first two bytes for the register address = then need to be transmitted. >=20 > I thought that was spelled out in the i2c spec fairly clearly=85 You are of course correct. > Do you have the data sheet showing this timing? I don't have one for the 8366RB, but the 8366 and 8366S chips appear to = follow the same timing. See=20 http://realtek.info/pdf/rtl8366_8369_datasheet_1-1.pdf (9.2, page 44) http://realtek.info/pdf/rtl8366s_8366sr_datasheet_vpre-1.4_20071022.pdf = (9.2, page 66) I think it would be beneficial to either remove this constraint in = iicconf.c entirely, or make it optional, so that we can use the = infrastructure for devices that "almost" speak I2C. Stefan --=20 Stefan Bethke Fon +49 151 14070811