From owner-freebsd-mips@freebsd.org Mon Nov 9 17:46:49 2015 Return-Path: Delivered-To: freebsd-mips@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id CB8CDA2A86C for ; Mon, 9 Nov 2015 17:46:49 +0000 (UTC) (envelope-from ian@freebsd.org) Received: from outbound1b.ore.mailhop.org (outbound1b.ore.mailhop.org [54.200.247.200]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id A0FAB1D0F for ; Mon, 9 Nov 2015 17:46:49 +0000 (UTC) (envelope-from ian@freebsd.org) Received: from ilsoft.org (unknown [73.34.117.227]) by outbound1.ore.mailhop.org (Halon Mail Gateway) with ESMTPSA; Mon, 9 Nov 2015 17:46:55 +0000 (UTC) Received: from rev (rev [172.22.42.240]) by ilsoft.org (8.14.9/8.14.9) with ESMTP id tA9Hkl18001326; Mon, 9 Nov 2015 10:46:47 -0700 (MST) (envelope-from ian@freebsd.org) Message-ID: <1447091207.91534.481.camel@freebsd.org> Subject: Re: CPU underload From: Ian Lepore To: Eugene Grosbein , Adrian Chadd Cc: "freebsd-mips@freebsd.org" Date: Mon, 09 Nov 2015 10:46:47 -0700 In-Reply-To: <5640DB0E.8010005@grosbein.net> References: <56348063.3090508@grosbein.net> <563500FC.8020201@grosbein.net> <5635148B.2070307@grosbein.net> <56351AA6.80903@grosbein.net> <563523CA.3040207@grosbein.net> <56367686.4090801@grosbein.net> <563707A0.3040700@grosbein.net> <56370E1D.3040801@grosbein.net> <563F5630.2000407@grosbein.net> <563F938B.3070707@grosbein.net> <1447090771.91534.477.camel@freebsd.org> <5640DB0E.8010005@grosbein.net> Content-Type: text/plain; charset="us-ascii" X-Mailer: Evolution 3.16.5 FreeBSD GNOME Team Port Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Nov 2015 17:46:49 -0000 On Tue, 2015-11-10 at 00:42 +0700, Eugene Grosbein wrote: > On 10.11.2015 00:39, Ian Lepore wrote: > > On Sun, 2015-11-08 at 11:23 -0800, Adrian Chadd wrote: > > > ok, what's the l1 cache size reported at boot up? > > > > > > I think I may just bump them all to 64. > > > > 64 is not some kind of magic panacea. The value needs to be set to > > the > > cache line size for the runtime platform. If the right value is > > 32, > > then setting it to 64 will just waste memory. > > Is it for instruction cache or for data cache? Only the data cache size matters for USB_HOST_ALIGN. -- Ian