From owner-svn-src-head@freebsd.org Sat Jul 28 12:50:11 2018 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id C356F10507E9; Sat, 28 Jul 2018 12:50:10 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 79D788CE0A; Sat, 28 Jul 2018 12:50:10 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 43F3726D55; Sat, 28 Jul 2018 12:50:10 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id w6SCoAI9090262; Sat, 28 Jul 2018 12:50:10 GMT (envelope-from andrew@FreeBSD.org) Received: (from andrew@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id w6SCo9VX090259; Sat, 28 Jul 2018 12:50:09 GMT (envelope-from andrew@FreeBSD.org) Message-Id: <201807281250.w6SCo9VX090259@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: andrew set sender to andrew@FreeBSD.org using -f From: Andrew Turner Date: Sat, 28 Jul 2018 12:50:09 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r336829 - in head/sys: arm/arm conf X-SVN-Group: head X-SVN-Commit-Author: andrew X-SVN-Commit-Paths: in head/sys: arm/arm conf X-SVN-Commit-Revision: 336829 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 28 Jul 2018 12:50:11 -0000 Author: andrew Date: Sat Jul 28 12:50:09 2018 New Revision: 336829 URL: https://svnweb.freebsd.org/changeset/base/336829 Log: Only build the cache handling code we need when building the arm ELF trampoline. Modified: head/sys/arm/arm/cpufunc_asm_armv5_ec.S head/sys/arm/arm/cpufunc_asm_sheeva.S head/sys/conf/Makefile.arm Modified: head/sys/arm/arm/cpufunc_asm_armv5_ec.S ============================================================================== --- head/sys/arm/arm/cpufunc_asm_armv5_ec.S Sat Jul 28 12:20:42 2018 (r336828) +++ head/sys/arm/arm/cpufunc_asm_armv5_ec.S Sat Jul 28 12:50:09 2018 (r336829) @@ -39,6 +39,7 @@ #include __FBSDID("$FreeBSD$"); +#ifndef ELF_TRAMPOLINE /* * Functions to set the MMU Translation Table Base register * @@ -192,6 +193,7 @@ ENTRY(armv5_ec_idcache_wbinv_range) mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ RET END(armv5_ec_idcache_wbinv_range) +#endif /* !ELF_TRAMPOLINE */ ENTRY_NP(armv5_ec_idcache_wbinv_all) .Larmv5_ec_idcache_wbinv_all: @@ -204,6 +206,7 @@ ENTRY_NP(armv5_ec_idcache_wbinv_all) /* Fall through to purge Dcache. */ END(armv5_ec_idcache_wbinv_all) +#ifndef ELF_TRAMPOLINE ENTRY(armv5_ec_dcache_wbinv_all) .Larmv5_ec_dcache_wbinv_all: 1: mrc p15, 0, APSR_nzcv, c7, c14, 3 /* Test, clean and invalidate DCache */ @@ -211,4 +214,4 @@ ENTRY(armv5_ec_dcache_wbinv_all) mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ RET END(armv5_ec_dcache_wbinv_all) - +#endif Modified: head/sys/arm/arm/cpufunc_asm_sheeva.S ============================================================================== --- head/sys/arm/arm/cpufunc_asm_sheeva.S Sat Jul 28 12:20:42 2018 (r336828) +++ head/sys/arm/arm/cpufunc_asm_sheeva.S Sat Jul 28 12:50:09 2018 (r336829) @@ -35,6 +35,7 @@ __FBSDID("$FreeBSD$"); #include #include +#ifndef ELF_TRAMPOLINE .Lsheeva_cache_line_size: .word _C_LABEL(arm_pdcache_line_size) .Lsheeva_asm_page_mask: @@ -376,6 +377,7 @@ ENTRY(sheeva_l2cache_wb_range) ldr lr, [sp], #4 RET END(sheeva_l2cache_wb_range) +#endif /* !ELF_TRAMPOLINE */ ENTRY(sheeva_l2cache_wbinv_all) /* Disable irqs */ @@ -393,6 +395,7 @@ ENTRY(sheeva_l2cache_wbinv_all) RET END(sheeva_l2cache_wbinv_all) +#ifndef ELF_TRAMPOLINE /* This function modifies register value as follows: * * arg1 arg EFFECT (bit value saved into register) @@ -418,4 +421,4 @@ ENTRY(sheeva_cpu_sleep) mcr p15, 0, r0, c7, c0, 4 /* Wait for interrupt */ mov pc, lr END(sheeva_cpu_sleep) - +#endif /* !ELF_TRAMPOLINE */ Modified: head/sys/conf/Makefile.arm ============================================================================== --- head/sys/conf/Makefile.arm Sat Jul 28 12:20:42 2018 (r336828) +++ head/sys/conf/Makefile.arm Sat Jul 28 12:50:09 2018 (r336829) @@ -73,8 +73,6 @@ SYSTEM_LD_TAIL +=;sed s/" + SIZEOF_HEADERS"// ldscript rm ${FULLKERNEL}.noheader FILES_CPU_FUNC = \ - $S/$M/$M/cpufunc_asm_arm9.S \ - $S/$M/$M/cpufunc_asm.S \ $S/$M/$M/cpufunc_asm_armv5_ec.S \ $S/$M/$M/cpufunc_asm_sheeva.S