From owner-svn-src-all@FreeBSD.ORG Fri Feb 27 11:13:47 2015 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 47303282; Fri, 27 Feb 2015 11:13:47 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 326C8BBB; Fri, 27 Feb 2015 11:13:47 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.9/8.14.9) with ESMTP id t1RBDkiL017780; Fri, 27 Feb 2015 11:13:46 GMT (envelope-from kib@FreeBSD.org) Received: (from kib@localhost) by svn.freebsd.org (8.14.9/8.14.9/Submit) id t1RBDkrs017779; Fri, 27 Feb 2015 11:13:46 GMT (envelope-from kib@FreeBSD.org) Message-Id: <201502271113.t1RBDkrs017779@svn.freebsd.org> X-Authentication-Warning: svn.freebsd.org: kib set sender to kib@FreeBSD.org using -f From: Konstantin Belousov Date: Fri, 27 Feb 2015 11:13:46 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r279352 - head/sys/x86/x86 X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Feb 2015 11:13:47 -0000 Author: kib Date: Fri Feb 27 11:13:46 2015 New Revision: 279352 URL: https://svnweb.freebsd.org/changeset/base/279352 Log: Since all generations of Intel CPUs have errata which causes hang on the cache line flush in the LAPIC page, keep direct map page covering LAPIC mapped uncached. To have the (incomplete) check for the LAPIC range in pmap_invalidate_cache_range() working, lapic_paddr must be initialized in x2APIC mode too. Sponsored by: The FreeBSD Foundation MFC after: 2 months Modified: head/sys/x86/x86/local_apic.c Modified: head/sys/x86/x86/local_apic.c ============================================================================== --- head/sys/x86/x86/local_apic.c Fri Feb 27 07:39:09 2015 (r279351) +++ head/sys/x86/x86/local_apic.c Fri Feb 27 11:13:46 2015 (r279352) @@ -388,16 +388,21 @@ native_lapic_init(vm_paddr_t addr) int i, arat; /* - * Enable x2APIC mode if possible, otherwise map the local - * APIC registers page. + * Enable x2APIC mode if possible. Map the local APIC + * registers page. + * + * Keep the LAPIC registers page mapped uncached for x2APIC + * mode too, to have direct map page attribute set to + * uncached. This is needed to work around CPU errata present + * on all Intel processors. */ KASSERT(trunc_page(addr) == addr, ("local APIC not aligned on a page boundary")); + lapic_paddr = addr; + lapic_map = pmap_mapdev(addr, PAGE_SIZE); if (x2apic_mode) { native_lapic_enable_x2apic(); - } else { - lapic_paddr = addr; - lapic_map = pmap_mapdev(addr, PAGE_SIZE); + lapic_map = NULL; } /* Setup the spurious interrupt handler. */