Date: Tue, 24 Dec 2013 08:18:23 -0600 From: Nathan Whitehorn <nwhitehorn@freebsd.org> To: freebsd-mips@freebsd.org Subject: mips_pic_if branch Message-ID: <52B997AF.70407@freebsd.org>
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I spent a little while trying to convert MIPS to use an interrupt domain system that is orthogonal to the bus topology. The goal, from my end, is to clean up some hacks in dev/fdt; the code is adapted with few changes from PowerPC, which has supported this for a while. The changes should provide a great deal more flexibility in terms of interrupt handling, in particular by allowing discrete PIC drivers that handle their own interrupt setup and configuration, while simultaneously reducing code duplication. The wrinkle is that I don't have any MIPS hardware and can only test in QEMU. So I'd appreciate any tests or comments. The branch can be found at: svn://svn.freebsd.org/base/user/nwhitehorn/mips_pic_if The BERI kernels I suspect are broken due to some features I could not figure out. Everything else should, in principle, work. The general layout of how this works is as follows: - An individual PIC implements a set of KOBJ methods that map an IRQ line to an opaque "vector" number and control masking/unmasking etc. When an interrupt is taken, either through the PIC_DISPATCH method or a cascaded interrupt via the PIC's IRQ line, the PIC calls mips_dispatch_intr(vector, trapframe) to trigger interrupt processing. - Interrupt domains are mapped using an interrupt domain identifier number (usually the iparent phandle for FDT systems) and an IRQ line. The function mips_get_irq() returns an opaque number that uniquely describes this interrupt system-wide. - Each PIC registers itself using mips_register_pic() in its attach method with the system. Note that this can happen either before or after its child interrupts are configured -- the code in intr_machdep.c delays all interrupt configuration until the relevant PIC device attached. -Nathan
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