From owner-svn-src-head@freebsd.org Mon Jun 8 08:51:53 2020 Return-Path: Delivered-To: svn-src-head@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id 69529347C25; Mon, 8 Jun 2020 08:51:53 +0000 (UTC) (envelope-from arichardson@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 49gRnj2CRFz3g9C; Mon, 8 Jun 2020 08:51:53 +0000 (UTC) (envelope-from arichardson@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 472EF21DE3; Mon, 8 Jun 2020 08:51:53 +0000 (UTC) (envelope-from arichardson@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id 0588pr3e010083; Mon, 8 Jun 2020 08:51:53 GMT (envelope-from arichardson@FreeBSD.org) Received: (from arichardson@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id 0588prB1010082; Mon, 8 Jun 2020 08:51:53 GMT (envelope-from arichardson@FreeBSD.org) Message-Id: <202006080851.0588prB1010082@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: arichardson set sender to arichardson@FreeBSD.org using -f From: Alex Richardson Date: Mon, 8 Jun 2020 08:51:53 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r361903 - head/sys/riscv/riscv X-SVN-Group: head X-SVN-Commit-Author: arichardson X-SVN-Commit-Paths: head/sys/riscv/riscv X-SVN-Commit-Revision: 361903 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.33 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 08 Jun 2020 08:51:53 -0000 Author: arichardson Date: Mon Jun 8 08:51:52 2020 New Revision: 361903 URL: https://svnweb.freebsd.org/changeset/base/361903 Log: RISC-V: handle DTB aligned to less than 2MB By default OpenSBI and BBL will pass the DTB at a 2MB-aligned address. However, by default there are no 2MB aligned regions between the SBI and the kernel, so we have to choose a 2MB aligned region after the kernel. OpenSBI defaults to placing the DTB 32MB after the start of the kernel but this is not sufficient for a kernel with a large MFS embedded. We could increase this offset to a larger number (e.g. 64/128/256) but that imposes restrictions on the minimum RAM size. Another solution would be to place the DTB between OpenSBI and the kernel at 1MB alignment, but current locore.S code assumes 2MB alignment. With this change I can now boot on QEMU with an OpenSBI configured to store the DTB at an offset of 1MB. See also https://github.com/riscv/opensbi/issues/169 Reviewed By: mhorne Differential Revision: https://reviews.freebsd.org/D25151 Modified: head/sys/riscv/riscv/locore.S Modified: head/sys/riscv/riscv/locore.S ============================================================================== --- head/sys/riscv/riscv/locore.S Mon Jun 8 02:42:41 2020 (r361902) +++ head/sys/riscv/riscv/locore.S Mon Jun 8 08:51:52 2020 (r361903) @@ -139,6 +139,8 @@ _start: lla s1, pagetable_l2_devmap mv s2, a1 srli s2, s2, PAGE_SHIFT + /* Mask off any bits that aren't aligned */ + andi s2, s2, ~((1 << (PTE_PPN1_S - PTE_PPN0_S)) - 1) li t0, (PTE_KERN) slli t2, s2, PTE_PPN0_S /* << PTE_PPN0_S */ @@ -214,6 +216,10 @@ va: sd t0, RISCV_BOOTPARAMS_KERN_STACK(sp) li t0, (VM_EARLY_DTB_ADDRESS) + /* Add offset of DTB within superpage */ + li t1, (L2_OFFSET) + and t1, a1, t1 + add t0, t0, t1 sd t0, RISCV_BOOTPARAMS_DTBP_VIRT(sp) mv a0, sp