From owner-svn-src-all@FreeBSD.ORG Mon May 6 13:52:50 2013 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by hub.freebsd.org (Postfix) with ESMTP id D7AE3783; Mon, 6 May 2013 13:52:50 +0000 (UTC) (envelope-from gber@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) by mx1.freebsd.org (Postfix) with ESMTP id B8F9B756; Mon, 6 May 2013 13:52:50 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.6/8.14.6) with ESMTP id r46DqoEG011423; Mon, 6 May 2013 13:52:50 GMT (envelope-from gber@svn.freebsd.org) Received: (from gber@localhost) by svn.freebsd.org (8.14.6/8.14.5/Submit) id r46DqoRO011420; Mon, 6 May 2013 13:52:50 GMT (envelope-from gber@svn.freebsd.org) Message-Id: <201305061352.r46DqoRO011420@svn.freebsd.org> From: Grzegorz Bernacki Date: Mon, 6 May 2013 13:52:50 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r250292 - in head/sys/arm/mv: . armadaxp X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 06 May 2013 13:52:50 -0000 Author: gber Date: Mon May 6 13:52:49 2013 New Revision: 250292 URL: http://svnweb.freebsd.org/changeset/base/250292 Log: Initialize L2 cache for Armada XP. Obtained from: Semihalf Modified: head/sys/arm/mv/armadaxp/armadaxp.c head/sys/arm/mv/armadaxp/std.armadaxp head/sys/arm/mv/mv_machdep.c Modified: head/sys/arm/mv/armadaxp/armadaxp.c ============================================================================== --- head/sys/arm/mv/armadaxp/armadaxp.c Mon May 6 13:34:36 2013 (r250291) +++ head/sys/arm/mv/armadaxp/armadaxp.c Mon May 6 13:52:49 2013 (r250292) @@ -36,6 +36,7 @@ __FBSDID("$FreeBSD$"); #include #include +#include #include #include @@ -51,6 +52,33 @@ __FBSDID("$FreeBSD$"); static uint32_t count_l2clk(void); +#define ARMADAXP_L2_BASE (MV_BASE + 0x8000) +#define ARMADAXP_L2_CTRL 0x100 +#define L2_ENABLE (1 << 0) +#define ARMADAXP_L2_AUX_CTRL 0x104 +#define L2_WBWT_MODE_MASK (3 << 0) +#define L2_WBWT_MODE_PAGE 0 +#define L2_WBWT_MODE_WB 1 +#define L2_WBWT_MODE_WT 2 +#define L2_REP_STRAT_MASK (3 << 27) +#define L2_REP_STRAT_LSFR (1 << 27) +#define L2_REP_STRAT_SEMIPLRU (3 << 27) + +#define ARMADAXP_L2_CNTR_CTRL 0x200 +#define ARMADAXP_L2_CNTR_CONF(x) (0x204 + (x) * 0xc) +#define ARMADAXP_L2_CNTR2_VAL_LOW (0x208 + (x) * 0xc) +#define ARMADAXP_L2_CNTR2_VAL_HI (0x20c + (x) * 0xc) + +#define ARMADAXP_L2_INT_CAUSE 0x220 + +#define ARMADAXP_L2_SYNC_BARRIER 0x700 +#define ARMADAXP_L2_INV_WAY 0x778 +#define ARMADAXP_L2_CLEAN_WAY 0x7BC +#define ARMADAXP_L2_FLUSH_PHYS 0x7F0 +#define ARMADAXP_L2_FLUSH_WAY 0x7FC + +#define COHER_FABRIC_CFU 0x228 + /* XXX Make gpio driver optional and remove it */ struct resource_spec mv_gpio_res[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, @@ -160,3 +188,76 @@ get_l2clk(void) return (l2clk_freq); } +void armadaxp_l2_init(void); +void armadaxp_l2_idcache_inv_all(void); + +#define ALL_WAYS 0xffffffff + +/* L2 cache configuration registers */ +static uint32_t +read_l2_cache(uint32_t reg) +{ + + return (bus_space_read_4(fdtbus_bs_tag, ARMADAXP_L2_BASE, reg)); +} + +static void +write_l2_cache(uint32_t reg, uint32_t val) +{ + + bus_space_write_4(fdtbus_bs_tag, ARMADAXP_L2_BASE, reg, val); +} + +void +armadaxp_l2_idcache_inv_all(void) +{ + write_l2_cache(ARMADAXP_L2_INV_WAY, ALL_WAYS); +} + +void +armadaxp_l2_init(void) +{ + u_int32_t reg; + + /* Set L2 policy */ + reg = read_l2_cache(ARMADAXP_L2_AUX_CTRL); + reg &= ~(L2_WBWT_MODE_MASK); + reg &= ~(L2_REP_STRAT_MASK); + reg |= L2_REP_STRAT_SEMIPLRU; + reg |= L2_WBWT_MODE_WT; + write_l2_cache(ARMADAXP_L2_AUX_CTRL, reg); + + /* Invalidate l2 cache */ + armadaxp_l2_idcache_inv_all(); + + /* Clear pending L2 interrupts */ + write_l2_cache(ARMADAXP_L2_INT_CAUSE, 0x1ff); + + /* Enable Cache and TLB maintenance broadcast */ + __asm__ __volatile__ ("mrc p15, 1, %0, c15, c2, 0" : "=r"(reg)); + reg |= (1 << 8); + __asm__ __volatile__ ("mcr p15, 1, %0, c15, c2, 0" : :"r"(reg)); + + /* Enable l2 cache */ + reg = read_l2_cache(ARMADAXP_L2_CTRL); + write_l2_cache(ARMADAXP_L2_CTRL, reg | L2_ENABLE); + + /* + * For debug purposes + * Configure and enable counter + */ + write_l2_cache(ARMADAXP_L2_CNTR_CONF(0), 0xf0000 | (4 << 2)); + write_l2_cache(ARMADAXP_L2_CNTR_CONF(1), 0xf0000 | (2 << 2)); + write_l2_cache(ARMADAXP_L2_CNTR_CTRL, 0x303); + + /* + * Enable Cache maintenance operation propagation in coherency fabric + * Change point of coherency and point of unification to DRAM. + */ + reg = bus_space_read_4(fdtbus_bs_tag, MV_MBUS_BRIDGE_BASE, + COHER_FABRIC_CFU); + reg |= (1 << 17) | (1 << 18); + bus_space_write_4(fdtbus_bs_tag, MV_MBUS_BRIDGE_BASE, COHER_FABRIC_CFU, + reg); +} + Modified: head/sys/arm/mv/armadaxp/std.armadaxp ============================================================================== --- head/sys/arm/mv/armadaxp/std.armadaxp Mon May 6 13:34:36 2013 (r250291) +++ head/sys/arm/mv/armadaxp/std.armadaxp Mon May 6 13:52:49 2013 (r250292) @@ -13,3 +13,5 @@ options KERNPHYSADDR=0x00f00000 options KERNVIRTADDR=0xc0f00000 options PHYSADDR=0x00000000 options STARTUP_PAGETABLE_ADDR=0x00100000 + +options ARM_L2_PIPT Modified: head/sys/arm/mv/mv_machdep.c ============================================================================== --- head/sys/arm/mv/mv_machdep.c Mon May 6 13:34:36 2013 (r250291) +++ head/sys/arm/mv/mv_machdep.c Mon May 6 13:52:49 2013 (r250292) @@ -61,6 +61,9 @@ __FBSDID("$FreeBSD$"); #include static int platform_mpp_init(void); +#if defined(SOC_MV_ARMADAXP) +void armadaxp_l2_init(void); +#endif #define MPP_PIN_MAX 68 #define MPP_PIN_CELLS 2 @@ -233,6 +236,9 @@ initarm_late_init(void) /* Disable watchdog and timers */ write_cpu_ctrl(CPU_TIMERS_BASE + CPU_TIMER_CONTROL, 0); #endif +#if defined(SOC_MV_ARMADAXP) + armadaxp_l2_init(); +#endif } #define FDT_DEVMAP_MAX (MV_WIN_CPU_MAX + 2)