From owner-freebsd-arm@freebsd.org Fri Aug 28 13:07:36 2015 Return-Path: Delivered-To: freebsd-arm@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id BE94C9C4942 for ; Fri, 28 Aug 2015 13:07:36 +0000 (UTC) (envelope-from prvs=6759bbf6f=julien.grall@citrix.com) Received: from SMTP.CITRIX.COM (smtp.citrix.com [66.165.176.89]) (using TLSv1 with cipher RC4-SHA (128/128 bits)) (Client CN "mail.citrix.com", Issuer "Verizon Public SureServer CA G14-SHA2" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 559116CE for ; Fri, 28 Aug 2015 13:07:35 +0000 (UTC) (envelope-from prvs=6759bbf6f=julien.grall@citrix.com) X-IronPort-AV: E=Sophos;i="5.17,424,1437436800"; d="scan'208";a="295519169" Message-ID: <55E05CC5.4040907@citrix.com> Date: Fri, 28 Aug 2015 14:06:13 +0100 From: Julien Grall User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Icedove/31.8.0 MIME-Version: 1.0 To: Mihai Carabas , Zbigniew Bodek CC: "freebsd-arm@freebsd.org" Subject: Re: GIC - interrupts interpretation in DTS/FDT References: In-Reply-To: Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-DLP: MIA2 X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: "Porting FreeBSD to ARM processors." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 28 Aug 2015 13:07:36 -0000 Hi, On 28/08/15 09:40, Mihai Carabas wrote: > On Fri, Aug 28, 2015 at 11:35 AM, Zbigniew Bodek wrote: > >> Hello Mihai, >> >> This documents may be helpful: >> >> https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/arm/gic.txt >> >> The meaning of each interrupt cell (for ARM GIC) is described there. >> >> Thank you for pointing me out that document. > > The problem I was asking was specific to the FreeBSD gic code: > """ > 165 >------->------- * The hardware only supports active-high-level or > rising-edge. > 166 >------->------- */ > 167 >------->-------if (fdt32_to_cpu(intr[2]) & 0x0a) { > 168 >------->------->-------printf("unsupported trigger/polarity > configuration " > 169 >------->------->------- "0x%2x\n", fdt32_to_cpu(intr[2]) & 0x0f); > 170 >------->------->-------return (ENOTSUP); > 171 >------->-------} > """ > > It is verified the not supported bits in both cases (PPIs and SPIs) and I > didn't understand why. Probably a bug. It's a bug, based on the documentation pointed by Zbigniew this check should only be done for SPIs. I hit this problem when porting FreeBSD as Xen ARM guest because our Xen interrupt is a PPI active-low level-sentive. I got a patch which I carry in my branch but never took the time to upstream it: --- a/sys/arm/arm/gic.c +++ b/sys/arm/arm/gic.c @@ -221,15 +221,16 @@ gic_decode_fdt(uint32_t iparent, uint32_t *intr, int *interrupt, * 2 = high-to-low edge triggered * 4 = active high level-sensitive * 8 = active low level-sensitive - * The hardware only supports active-high-level or rising-edge. + * The hardware only supports active-high-level or rising-edge + * for SPIs */ - if (fdt32_to_cpu(intr[2]) & 0x0a) { + if (*interrupt >= 32 && fdt32_to_cpu(intr[2]) & 0x0a) { printf("unsupported trigger/polarity configuration " "0x%2x\n", fdt32_to_cpu(intr[2]) & 0x0f); return (ENOTSUP); } *pol = INTR_POLARITY_CONFORM; - if (fdt32_to_cpu(intr[2]) & 0x01) + if (fdt32_to_cpu(intr[2]) & 0x03) *trig = INTR_TRIGGER_EDGE; else *trig = INTR_TRIGGER_LEVEL; Regards, -- Julien Grall