Date: Sat, 21 Jul 2012 23:48:45 GMT From: Adrian Chadd <adrian@FreeBSD.org> To: freebsd-gnats-submit@FreeBSD.org Subject: kern/170058: [cbb] cardbus slot is not functioning correctly after a resume Message-ID: <201207212348.q6LNmjO9084188@red.freebsd.org> Resent-Message-ID: <201207212350.q6LNo2SU061639@freefall.freebsd.org>
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>Number: 170058
>Category: kern
>Synopsis: [cbb] cardbus slot is not functioning correctly after a resume
>Confidential: no
>Severity: non-critical
>Priority: low
>Responsible: freebsd-bugs
>State: open
>Quarter:
>Keywords:
>Date-Required:
>Class: sw-bug
>Submitter-Id: current-users
>Arrival-Date: Sat Jul 21 23:50:02 UTC 2012
>Closed-Date:
>Last-Modified:
>Originator: Adrian Chadd
>Release: 9-STABLE
>Organization:
>Environment:
>Description:
There's a problem with the cbb device where it isn't correctly functioning after a suspend/resume cycle.
The main registers that are different are 0x18, 0x19, 0x1a - which are PCIR_PRIBUS_2, PCIR_SECBUS_2, PCIR_SUBBUS_2.
This is the register contents after a card is inserted and attached:
4c 10 56 ac 07 00 10 02 00 00 07 06 00 20 02 00
00 00 30 e4 a0 00 00 22 15 16 17 20 00 00 31 e4
00 f0 31 e4 00 f0 ff ff 00 00 00 00 fc ff ff ff
00 00 00 00 fc ff ff ff 00 00 00 00 ff 01 00 04
aa 17 12 20 01 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70 d0 44 08 00 00 00 00 00 00 00 00 02 10 d0 01
c0 03 64 40 00 00 00 00 00 00 00 00 00 00 00 00
01 00 12 fe 00 80 c0 00 13 08 00 00 0f 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
. and here it is after a suspend/resume:
4c 10 56 ac 07 00 10 02 00 00 07 06 00 20 02 00
00 00 30 e4 a0 00 00 22 00 00 00 20 00 f0 ff ff
00 00 00 00 00 f0 ff ff 00 00 00 00 fc ff ff ff
00 00 00 00 fc ff ff ff 00 00 00 00 ff 01 00 07
aa 17 12 20 01 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70 f0 44 08 00 00 00 00 00 00 00 00 02 10 d0 01
c0 03 64 40 00 00 00 00 00 00 00 00 00 00 00 00
01 00 12 fe 00 80 c0 00 03 08 00 00 0f 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>How-To-Repeat:
>Fix:
I've added something to the cbb code to work around this.
However, I wonder if the pci bridge code is the culprit. Ie, is pcib_cfg_restore() being called (via pcib_resume()) and writing garbage into the registers? I'm not sure.
It warrants further investigation!
Index: pccbb_pci.c
===================================================================
--- pccbb_pci.c (revision 238210)
+++ pccbb_pci.c (working copy)
@@ -457,6 +457,11 @@
{
uint32_t mux, sysctrl, reg;
+ /*
+ * Wake it up out of sleep
+ */
+ cbb_powerstate_d0(sc->dev);
+
/* Set CardBus latency timer */
if (pci_read_config(sc->dev, PCIR_SECLAT_1, 1) < 0x20)
pci_write_config(sc->dev, PCIR_SECLAT_1, 0x20, 1);
@@ -465,6 +470,11 @@
if (pci_read_config(sc->dev, PCIR_LATTIMER, 1) < 0x20)
pci_write_config(sc->dev, PCIR_LATTIMER, 0x20, 1);
+ /* Restore bus configuration */
+ pci_write_config(sc->dev, PCIR_PRIBUS_2, sc->pribus, 1);
+ pci_write_config(sc->dev, PCIR_SECBUS_2, sc->secbus, 1);
+ pci_write_config(sc->dev, PCIR_SUBBUS_2, sc->subbus, 1);
+
/* Enable memory access */
PCI_MASK_CONFIG(sc->dev, PCIR_COMMAND,
| PCIM_CMD_MEMEN
>Release-Note:
>Audit-Trail:
>Unformatted:
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