From owner-svn-src-all@FreeBSD.ORG Thu Aug 23 14:27:46 2012 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id B46CA106567F; Thu, 23 Aug 2012 14:27:46 +0000 (UTC) (envelope-from jhb@freebsd.org) Received: from bigwig.baldwin.cx (bigknife-pt.tunnel.tserv9.chi1.ipv6.he.net [IPv6:2001:470:1f10:75::2]) by mx1.freebsd.org (Postfix) with ESMTP id 89EDF8FC08; Thu, 23 Aug 2012 14:27:46 +0000 (UTC) Received: from jhbbsd.localnet (unknown [209.249.190.124]) by bigwig.baldwin.cx (Postfix) with ESMTPSA id E0734B91E; Thu, 23 Aug 2012 10:27:45 -0400 (EDT) From: John Baldwin To: Oleksandr Tymoshenko Date: Thu, 23 Aug 2012 07:46:57 -0400 User-Agent: KMail/1.13.5 (FreeBSD/8.2-CBSD-20110714-p17; KDE/4.5.5; amd64; ; ) References: <201208222248.q7MMmojL011382@svn.freebsd.org> In-Reply-To: <201208222248.q7MMmojL011382@svn.freebsd.org> MIME-Version: 1.0 Content-Type: Text/Plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <201208230746.57495.jhb@freebsd.org> X-Greylist: Sender succeeded SMTP AUTH, not delayed by milter-greylist-4.2.7 (bigwig.baldwin.cx); Thu, 23 Aug 2012 10:27:46 -0400 (EDT) Cc: svn-src-head@freebsd.org, svn-src-all@freebsd.org, src-committers@freebsd.org Subject: Re: svn commit: r239597 - head/sys/arm/arm X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 23 Aug 2012 14:27:46 -0000 On Wednesday, August 22, 2012 6:48:50 pm Oleksandr Tymoshenko wrote: > Author: gonzo > Date: Wed Aug 22 22:48:50 2012 > New Revision: 239597 > URL: http://svn.freebsd.org/changeset/base/239597 > > Log: > Do not change "cachable" attribute for DMA memory allocated with > BUS_DMA_COHERENT attribute > > The minimum unit for changing "cachable" attribute is page, so call > to pmap_change_attr effectively disable cache for all pages that newly > allocated DMA memory region spans on. The problem is that general-purpose > memory could reside on these pages too and disabling cache might affect > performance. Moreover ldrex/strex operators raise Data Abort exception > when accessing memory on page with "cachable" attribute off. > > BUS_DMA_COHERENT does nto require memory to be coherent. It just suggests > to do best effort for reducing synchronization overhead. Alternatively you could force an allocation with BUS_DMA_COHERENT to always allocate at least one page. Also, it is probably better to match what I recently did in x86 and use kmem_alloc_contig() or kmem_alloc_attr() for allocations with a custom memory attribute rather than using pmap_change_attr() directly. -- John Baldwin